2018-09-27 09:46:39 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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2018-09-28 14:59:46 +00:00
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/*
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Interface to FMC connector overview
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system_top 9009_FMC FMC FPGA
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-------------|--------------------------------|-----
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input ref_clk0_p, (DNI) FPGA_REF_CLK+ D4 FMC_HPC_GBTCLK0_M2C_P AD10
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input ref_clk0_n, (DNI) FPGA_REF_CLK- D5 FMC_HPC_GBTCLK0_M2C_N AD9
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input ref_clk1_p, FPGA_REF_CLK+ B20 FMC_HPC_GBTCLK1_M2C_P AA8
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input ref_clk1_n, FPGA_REF_CLK- B21 FMC_HPC_GBTCLK1_M2C_N AA7
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input rx_data_p[0], SERDOUT0+ A2 FMC_HPC_DP1_M2C_P AJ8
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input rx_data_n[0], SERDOUT0- A3 FMC_HPC_DP1_M2C_N AJ7
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input rx_data_p[1], SERDOUT1+ A6 FMC_HPC_DP2_M2C_P AG8
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input rx_data_n[1], SERDOUT1- A7 FMC_HPC_DP2_M2C_N AG7
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input rx_data_p[2], SERDOUT2+ C6 FMC_HPC_DP0_M2C_P AH10
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input rx_data_n[2], SERDOUT2- C7 FMC_HPC_DP0_M2C_N AH9
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input rx_data_p[3], SERDOUT3+ A10 FMC_HPC_DP3_M2C_P AE8
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input rx_data_n[3], SERDOUT3- A11 FMC_HPC_DP3_M2C_N AE7
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output tx_data_p[0], SERDIN0+ A22 FMC_HPC_DP1_C2M_P AK6
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output tx_data_n[0], SERDIN0- A23 FMC_HPC_DP1_C2M_N AK5
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output tx_data_p[1], SERDIN3+ A26 FMC_HPC_DP2_C2M_P AJ4
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output tx_data_n[1], SERDIN3- A27 FMC_HPC_DP2_C2M_N AJ3
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2019-06-05 13:37:34 +00:00
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output tx_data_p[2], SERDIN2+ C2 FMC_HPC_DP0_C2M_P AK10
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2018-09-28 14:59:46 +00:00
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output tx_data_n[2], SERDIN2- C3 FMC_HPC_DP0_C2M_N AK9
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output tx_data_p[3], SERDIN1+ A30 FMC_HPC_DP3_C2M_P AK2
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output tx_data_n[3], SERDIN1- A31 FMC_HPC_DP3_C2M_N AK1
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output rx_sync_p, SYNCINB0+ G9 FMC_HPC_LA03_P AH19
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output rx_sync_n, SYNCINB0- G10 FMC_HPC_LA03_N AJ19
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output rx_os_sync_p, SYNCINB1+ G27 FMC_HPC_LA25_P T29
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output rx_os_sync_n, SYNCINB1- G28 FMC_HPC_LA25_N U29
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input tx_sync_p, SYNCOUTB0+ H7 FMC_HPC_LA02_P AK17
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input tx_sync_n, SYNCOUTB0- H8 FMC_HPC_LA02_N AK18
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input tx_sync_1_p, SYNCOUTB1+ H28 FMC_HPC_LA24_P T30
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input tx_sync_1_n, SYNCOUTB1- H29 FMC_HPC_LA24_N U30
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input sysref_p, FPGA_SYSREF+ G6 FMC_HPC_LA00_CC_P AF20
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input sysref_n, FPGA_SYSREF- G7 FMC_HPC_LA00_CC_N AG20
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output sysref_out_p, FPGA_SYSREF_OUT+ D8 FMC_HPC_LA01_CC_P AG21
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output sysref_out_n, FPGA_SYSREF_OUT- D9 FMC_HPC_LA01_CC_N AH21
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output spi_csn_ad9528, SPI_CS1 D15 FMC_HPC_LA09_N AE21
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output spi_csn_adrv9009, SPI_CS0 D14 FMC_HPC_LA09_P AD21
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output spi_clk, SPI_CLK H13 FMC_HPC_LA07_P AJ23
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output spi_mosi, SPI_DIN H14 FMC_HPC_LA07_N AJ24
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input spi_miso, SPI_DOUT G12 FMC_HPC_LA08_P AF19
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inout ad9528_reset_b, FMC_CLK_RESETB D26 FMC_HPC_LA26_P R28
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inout ad9528_sysref_req, FMC_SYSREF_REQUEST D27 FMC_HPC_LA26_N T28
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inout adrv9009_tx1_enable, TX1_ENABLE D17 FMC_HPC_LA13_P AA22
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inout adrv9009_tx2_enable, TX2_ENABLE C18 FMC_HPC_LA14_P AC24
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inout adrv9009_rx1_enable, RX1_ENABLE D18 FMC_HPC_LA13_N AA23
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inout adrv9009_rx2_enable, RX2_ENABLE C19 FMC_HPC_LA14_N AD24
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2019-06-05 13:37:34 +00:00
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inout adrv9009_test, TEST H16 FMC_HPC_LA11_P AD23
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2018-09-28 14:59:46 +00:00
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inout adrv9009_reset_b, RESETB H10 FMC_HPC_LA04_P AJ20
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inout adrv9009_gpint, GP_INTERRUPT H11 FMC_HPC_LA04_N AK20
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inout adrv9009_gpio_00, GPIO_0 H19 FMC_HPC_LA15_P Y22
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inout adrv9009_gpio_01, GPIO_1 H20 FMC_HPC_LA15_N Y23
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inout adrv9009_gpio_02, GPIO_2 G18 FMC_HPC_LA16_P AA24
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inout adrv9009_gpio_03, GPIO_3 G19 FMC_HPC_LA16_N AB24
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inout adrv9009_gpio_04, GPIO_4 H25 FMC_HPC_LA21_P W29
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inout adrv9009_gpio_05, GPIO_5 H26 FMC_HPC_LA21_N W30
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inout adrv9009_gpio_06, GPIO_6 C22 FMC_HPC_LA18_CC_P W25
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inout adrv9009_gpio_07, GPIO_7 C23 FMC_HPC_LA18_CC_N W26
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inout adrv9009_gpio_08, GPIO_8 G25 FMC_HPC_LA22_N W28
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inout adrv9009_gpio_09, GPIO_9 H22 FMC_HPC_LA19_P T24
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inout adrv9009_gpio_10, GPIO_10 H23 FMC_HPC_LA19_N T25
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inout adrv9009_gpio_11, GPIO_11 G21 FMC_HPC_LA20_P U25
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inout adrv9009_gpio_12, GPIO_12 G22 FMC_HPC_LA20_N V26
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inout adrv9009_gpio_13, GPIO_13 G16 FMC_HPC_LA12_N AF24
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2019-06-05 13:37:34 +00:00
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inout adrv9009_gpio_14, GPIO_14 G15 FMC_HPC_LA12_P AF23
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2018-09-28 14:59:46 +00:00
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inout adrv9009_gpio_15, GPIO_15 G24 FMC_HPC_LA22_P V27
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inout adrv9009_gpio_16, GPIO_16 C11 FMC_HPC_LA06_N AH22
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inout adrv9009_gpio_17, GPIO_17 C10 FMC_HPC_LA06_P AG22
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inout adrv9009_gpio_18, GPIO_18 H17 FMC_HPC_LA11_N AE23
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*/
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2018-09-27 09:46:39 +00:00
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [14:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [23:0] hdmi_data,
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output spdif,
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inout iic_scl,
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inout iic_sda,
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input ref_clk0_p,
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input ref_clk0_n,
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input ref_clk1_p,
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input ref_clk1_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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output [ 3:0] tx_data_p,
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output [ 3:0] tx_data_n,
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output rx_sync_p,
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output rx_sync_n,
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output rx_os_sync_p,
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output rx_os_sync_n,
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input tx_sync_p,
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input tx_sync_n,
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input tx_sync_1_p,
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input tx_sync_1_n,
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input sysref_p,
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input sysref_n,
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output sysref_out_p,
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output sysref_out_n,
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output spi_csn_ad9528,
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output spi_csn_adrv9009,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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inout ad9528_reset_b,
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inout ad9528_sysref_req,
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inout adrv9009_tx1_enable,
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inout adrv9009_tx2_enable,
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inout adrv9009_rx1_enable,
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inout adrv9009_rx2_enable,
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inout adrv9009_test,
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inout adrv9009_reset_b,
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inout adrv9009_gpint,
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inout adrv9009_gpio_00,
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inout adrv9009_gpio_01,
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inout adrv9009_gpio_02,
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inout adrv9009_gpio_03,
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inout adrv9009_gpio_04,
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inout adrv9009_gpio_05,
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inout adrv9009_gpio_06,
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inout adrv9009_gpio_07,
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inout adrv9009_gpio_15,
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inout adrv9009_gpio_08,
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inout adrv9009_gpio_09,
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inout adrv9009_gpio_10,
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inout adrv9009_gpio_11,
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inout adrv9009_gpio_12,
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inout adrv9009_gpio_14,
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inout adrv9009_gpio_13,
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inout adrv9009_gpio_17,
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inout adrv9009_gpio_16,
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inout adrv9009_gpio_18,
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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output [13:0] ddr3_addr,
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output [ 2:0] ddr3_ba,
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output ddr3_cas_n,
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output [ 0:0] ddr3_ck_n,
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output [ 0:0] ddr3_ck_p,
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output [ 0:0] ddr3_cke,
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output [ 0:0] ddr3_cs_n,
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output [ 7:0] ddr3_dm,
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inout [63:0] ddr3_dq,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 7:0] ddr3_dqs_p,
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output [ 0:0] ddr3_odt,
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output ddr3_ras_n,
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output ddr3_reset_n,
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output ddr3_we_n);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire ref_clk0;
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wire ref_clk1;
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wire rx_sync;
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wire rx_os_sync;
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wire tx_sync;
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wire tx_sync_1;
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wire sysref;
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wire sysref_out;
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assign sysref_out = 0;
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assign gpio_i[63:60] = gpio_o[63:60];
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assign gpio_i[31:15] = gpio_o[31:15];
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// instantiations
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (ref_clk0_p),
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.IB (ref_clk0_n),
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.O (ref_clk0),
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.ODIV2 ());
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IBUFDS_GTE2 i_ibufds_ref_clk1 (
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.CEB (1'd0),
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.I (ref_clk1_p),
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.IB (ref_clk1_n),
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.O (ref_clk1),
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.ODIV2 ());
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2022-02-14 08:15:59 +00:00
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BUFG i_bufg_ref_clk (
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.I (ref_clk1),
|
|
|
|
|
.O (ref_clk1_bufg));
|
|
|
|
|
|
2018-09-27 09:46:39 +00:00
|
|
|
OBUFDS i_obufds_rx_sync (
|
|
|
|
|
.I (rx_sync),
|
|
|
|
|
.O (rx_sync_p),
|
|
|
|
|
.OB (rx_sync_n));
|
|
|
|
|
|
|
|
|
|
OBUFDS i_obufds_rx_os_sync (
|
|
|
|
|
.I (rx_os_sync),
|
|
|
|
|
.O (rx_os_sync_p),
|
|
|
|
|
.OB (rx_os_sync_n));
|
|
|
|
|
|
|
|
|
|
OBUFDS i_obufds_sysref_out (
|
|
|
|
|
.I (sysref_out),
|
|
|
|
|
.O (sysref_out_p),
|
|
|
|
|
.OB (sysref_out_n));
|
|
|
|
|
|
|
|
|
|
IBUFDS i_ibufds_tx_sync (
|
|
|
|
|
.I (tx_sync_p),
|
|
|
|
|
.IB (tx_sync_n),
|
|
|
|
|
.O (tx_sync));
|
|
|
|
|
|
|
|
|
|
IBUFDS i_ibufds_tx_sync_1 (
|
|
|
|
|
.I (tx_sync_1_p),
|
|
|
|
|
.IB (tx_sync_1_n),
|
|
|
|
|
.O (tx_sync_1));
|
|
|
|
|
|
|
|
|
|
IBUFDS i_ibufds_sysref (
|
|
|
|
|
.I (sysref_p),
|
|
|
|
|
.IB (sysref_n),
|
|
|
|
|
.O (sysref));
|
|
|
|
|
|
|
|
|
|
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
|
|
|
|
|
.dio_t ({gpio_t[59:32]}),
|
|
|
|
|
.dio_i ({gpio_o[59:32]}),
|
|
|
|
|
.dio_o ({gpio_i[59:32]}),
|
|
|
|
|
.dio_p ({ ad9528_reset_b, // 59
|
|
|
|
|
ad9528_sysref_req, // 58
|
|
|
|
|
adrv9009_tx1_enable, // 57
|
|
|
|
|
adrv9009_tx2_enable, // 56
|
|
|
|
|
adrv9009_rx1_enable, // 55
|
|
|
|
|
adrv9009_rx2_enable, // 54
|
|
|
|
|
adrv9009_test, // 53
|
|
|
|
|
adrv9009_reset_b, // 52
|
|
|
|
|
adrv9009_gpint, // 51
|
|
|
|
|
adrv9009_gpio_00, // 50
|
|
|
|
|
adrv9009_gpio_01, // 49
|
|
|
|
|
adrv9009_gpio_02, // 48
|
|
|
|
|
adrv9009_gpio_03, // 47
|
|
|
|
|
adrv9009_gpio_04, // 46
|
|
|
|
|
adrv9009_gpio_05, // 45
|
|
|
|
|
adrv9009_gpio_06, // 44
|
|
|
|
|
adrv9009_gpio_07, // 43
|
|
|
|
|
adrv9009_gpio_15, // 42
|
|
|
|
|
adrv9009_gpio_08, // 41
|
|
|
|
|
adrv9009_gpio_09, // 40
|
|
|
|
|
adrv9009_gpio_10, // 39
|
|
|
|
|
adrv9009_gpio_11, // 38
|
|
|
|
|
adrv9009_gpio_12, // 37
|
|
|
|
|
adrv9009_gpio_14, // 36
|
|
|
|
|
adrv9009_gpio_13, // 35
|
|
|
|
|
adrv9009_gpio_17, // 34
|
|
|
|
|
adrv9009_gpio_16, // 33
|
|
|
|
|
adrv9009_gpio_18})); // 32
|
|
|
|
|
|
|
|
|
|
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
|
|
|
|
.dio_t (gpio_t[14:0]),
|
|
|
|
|
.dio_i (gpio_o[14:0]),
|
|
|
|
|
.dio_o (gpio_i[14:0]),
|
|
|
|
|
.dio_p (gpio_bd));
|
|
|
|
|
|
|
|
|
|
system_wrapper i_system_wrapper (
|
|
|
|
|
.dac_fifo_bypass (gpio_o[60]),
|
2019-06-24 15:26:34 +00:00
|
|
|
.adc_fir_filter_active (gpio_o[61]),
|
|
|
|
|
.dac_fir_filter_active (gpio_o[62]),
|
2018-09-27 09:46:39 +00:00
|
|
|
.ddr3_addr (ddr3_addr),
|
|
|
|
|
.ddr3_ba (ddr3_ba),
|
|
|
|
|
.ddr3_cas_n (ddr3_cas_n),
|
|
|
|
|
.ddr3_ck_n (ddr3_ck_n),
|
|
|
|
|
.ddr3_ck_p (ddr3_ck_p),
|
|
|
|
|
.ddr3_cke (ddr3_cke),
|
|
|
|
|
.ddr3_cs_n (ddr3_cs_n),
|
|
|
|
|
.ddr3_dm (ddr3_dm),
|
|
|
|
|
.ddr3_dq (ddr3_dq),
|
|
|
|
|
.ddr3_dqs_n (ddr3_dqs_n),
|
|
|
|
|
.ddr3_dqs_p (ddr3_dqs_p),
|
|
|
|
|
.ddr3_odt (ddr3_odt),
|
|
|
|
|
.ddr3_ras_n (ddr3_ras_n),
|
|
|
|
|
.ddr3_reset_n (ddr3_reset_n),
|
|
|
|
|
.ddr3_we_n (ddr3_we_n),
|
|
|
|
|
.ddr_addr (ddr_addr),
|
|
|
|
|
.ddr_ba (ddr_ba),
|
|
|
|
|
.ddr_cas_n (ddr_cas_n),
|
|
|
|
|
.ddr_ck_n (ddr_ck_n),
|
|
|
|
|
.ddr_ck_p (ddr_ck_p),
|
|
|
|
|
.ddr_cke (ddr_cke),
|
|
|
|
|
.ddr_cs_n (ddr_cs_n),
|
|
|
|
|
.ddr_dm (ddr_dm),
|
|
|
|
|
.ddr_dq (ddr_dq),
|
|
|
|
|
.ddr_dqs_n (ddr_dqs_n),
|
|
|
|
|
.ddr_dqs_p (ddr_dqs_p),
|
|
|
|
|
.ddr_odt (ddr_odt),
|
|
|
|
|
.ddr_ras_n (ddr_ras_n),
|
|
|
|
|
.ddr_reset_n (ddr_reset_n),
|
|
|
|
|
.ddr_we_n (ddr_we_n),
|
|
|
|
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
|
|
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
|
|
|
.fixed_io_mio (fixed_io_mio),
|
|
|
|
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
|
|
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
|
|
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
|
|
|
.gpio_i (gpio_i),
|
|
|
|
|
.gpio_o (gpio_o),
|
|
|
|
|
.gpio_t (gpio_t),
|
|
|
|
|
.hdmi_data (hdmi_data),
|
|
|
|
|
.hdmi_data_e (hdmi_data_e),
|
|
|
|
|
.hdmi_hsync (hdmi_hsync),
|
|
|
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
|
|
|
.hdmi_vsync (hdmi_vsync),
|
|
|
|
|
.iic_main_scl_io (iic_scl),
|
|
|
|
|
.iic_main_sda_io (iic_sda),
|
|
|
|
|
.rx_data_0_n (rx_data_n[0]),
|
|
|
|
|
.rx_data_0_p (rx_data_p[0]),
|
|
|
|
|
.rx_data_1_n (rx_data_n[1]),
|
|
|
|
|
.rx_data_1_p (rx_data_p[1]),
|
|
|
|
|
.rx_data_2_n (rx_data_n[2]),
|
|
|
|
|
.rx_data_2_p (rx_data_p[2]),
|
|
|
|
|
.rx_data_3_n (rx_data_n[3]),
|
|
|
|
|
.rx_data_3_p (rx_data_p[3]),
|
|
|
|
|
.rx_ref_clk_0 (ref_clk1),
|
|
|
|
|
.rx_ref_clk_2 (ref_clk1),
|
|
|
|
|
.rx_sync_0 (rx_sync),
|
|
|
|
|
.rx_sync_2 (rx_os_sync),
|
|
|
|
|
.rx_sysref_0 (sysref),
|
|
|
|
|
.rx_sysref_2 (sysref),
|
|
|
|
|
.spdif (spdif),
|
|
|
|
|
.spi0_clk_i (spi_clk),
|
|
|
|
|
.spi0_clk_o (spi_clk),
|
2018-11-01 12:38:08 +00:00
|
|
|
.spi0_csn_0_o (spi_csn_ad9528),
|
|
|
|
|
.spi0_csn_1_o (spi_csn_adrv9009),
|
2018-09-27 09:46:39 +00:00
|
|
|
.spi0_csn_2_o (),
|
|
|
|
|
.spi0_csn_i (1'b1),
|
|
|
|
|
.spi0_sdi_i (spi_miso),
|
|
|
|
|
.spi0_sdo_i (spi_mosi),
|
|
|
|
|
.spi0_sdo_o (spi_mosi),
|
|
|
|
|
.spi1_clk_i (1'd0),
|
|
|
|
|
.spi1_clk_o (),
|
|
|
|
|
.spi1_csn_0_o (),
|
|
|
|
|
.spi1_csn_1_o (),
|
|
|
|
|
.spi1_csn_2_o (),
|
|
|
|
|
.spi1_csn_i (1'b1),
|
|
|
|
|
.spi1_sdi_i (1'd0),
|
|
|
|
|
.spi1_sdo_i (1'd0),
|
|
|
|
|
.spi1_sdo_o (),
|
|
|
|
|
.sys_clk_clk_n (sys_clk_n),
|
|
|
|
|
.sys_clk_clk_p (sys_clk_p),
|
|
|
|
|
.sys_rst(sys_rst),
|
|
|
|
|
.tx_data_0_n (tx_data_n[0]),
|
|
|
|
|
.tx_data_0_p (tx_data_p[0]),
|
|
|
|
|
.tx_data_1_n (tx_data_n[1]),
|
|
|
|
|
.tx_data_1_p (tx_data_p[1]),
|
|
|
|
|
.tx_data_2_n (tx_data_n[2]),
|
|
|
|
|
.tx_data_2_p (tx_data_p[2]),
|
|
|
|
|
.tx_data_3_n (tx_data_n[3]),
|
|
|
|
|
.tx_data_3_p (tx_data_p[3]),
|
|
|
|
|
.tx_ref_clk_0 (ref_clk1),
|
|
|
|
|
.tx_sync_0 (tx_sync),
|
2022-02-14 08:15:59 +00:00
|
|
|
.tx_sysref_0 (sysref),
|
|
|
|
|
.ref_clk (ref_clk1_bufg));
|
2018-09-27 09:46:39 +00:00
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
// ***************************************************************************
|
|
|
|
|
// ***************************************************************************
|
