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pluto_hdl_adi/library/axi_hdmi_tx/axi_hdmi_tx.v

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initial checkin
2014-02-28 19:26:22 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
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// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
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// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
initial checkin
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//
// ***************************************************************************
// ***************************************************************************
Add missing timescale annotations For consistent simulation behavior it is recommended to annotate all source files with a timescale. Add it to those where it is currently missing. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-27 07:14:54 +00:00
`timescale 1ns/100ps
all: Update verilog files to verilog-2001
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module axi_hdmi_tx #(
parameter ID = 0,
parameter CR_CB_N = 0,
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
parameter FPGA_TECHNOLOGY = 0,
axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type Update all carriers/projects bd for configurable video interface: - common zc702, zc706, zed - adrv9361z7035/ccfmc_lvds - imageon
2018-07-23 12:21:44 +00:00
parameter INTERFACE = "16_BIT",
all: Update verilog files to verilog-2001
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parameter OUT_CLK_POLARITY = 0) (
initial checkin
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// hdmi interface
all: Update verilog files to verilog-2001
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input hdmi_clk,
output hdmi_out_clk,
initial checkin
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// 16-bit interface
all: Update verilog files to verilog-2001
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output hdmi_16_hsync,
output hdmi_16_vsync,
output hdmi_16_data_e,
output [15:0] hdmi_16_data,
output [15:0] hdmi_16_es_data,
initial checkin
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// 24-bit interface
all: Update verilog files to verilog-2001
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output hdmi_24_hsync,
output hdmi_24_vsync,
output hdmi_24_data_e,
output [23:0] hdmi_24_data,
initial checkin
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// 36-bit interface
all: Update verilog files to verilog-2001
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output hdmi_36_hsync,
output hdmi_36_vsync,
output hdmi_36_data_e,
output [35:0] hdmi_36_data,
initial checkin
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// vdma interface
all: Update verilog files to verilog-2001
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input vdma_clk,
axi_hdmi_tx: Update to use ADI DMA The frame synchronization between axi_hdmi_tx and axi_dmac is based on the DMA(2D streaming) last signal. The last signal will be used as an end of frame signal marking the beginning of the future frame to be transferred by the DMA. Only after both HDMI and DMA are ready for a "new frame" data will be requested from the DMA. The datarate and CDC between the axi_dmac and axi_hdmi_tx cores will be handled by axi_hdmi_tx's DMA interface based on a backpressure mechanism.
2018-05-11 15:00:15 +00:00
input vdma_end_of_frame,
all: Update verilog files to verilog-2001
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input vdma_valid,
input [63:0] vdma_data,
output vdma_ready,
initial checkin
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// axi interface
all: Update verilog files to verilog-2001
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input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 06:01:40 +00:00
input [15:0] s_axi_awaddr,
all: Update verilog files to verilog-2001
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input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 06:01:40 +00:00
input [15:0] s_axi_araddr,
all: Update verilog files to verilog-2001
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input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
axi_hdmi_tx: Add parameter to configure the output clock polarity In order to maximize the window where it is safe to capture data we ideally want to launch data on the opposite edge to which it is captured. Since the edge on which data is captured depends on the connected device add a parameter that allows to configure the launching edge. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 09:36:49 +00:00
/* 0 = Launch on rising edge, 1 = Launch on falling edge */
initial checkin
2014-02-28 19:26:22 +00:00
axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type Update all carriers/projects bd for configurable video interface: - common zc702, zc706, zed - adrv9361z7035/ccfmc_lvds - imageon
2018-07-23 12:21:44 +00:00
localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0;
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
localparam XILINX_7SERIES = 1;
localparam XILINX_ULTRASCALE = 2;
axi_hdmi_tx: Add UltraScale+ architecture to Verilog
2021-10-08 11:36:55 +00:00
localparam XILINX_ULTRASCALE_PLUS = 3;
axi_hdmi_tx: Update parameter name
2019-03-27 16:28:37 +00:00
localparam INTEL_5SERIES = 101;
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
initial checkin
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// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_rst;
// internal signals
up/constr: independent read/write and local constraints
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wire up_wreq_s;
wire [13:0] up_waddr_s;
initial checkin
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wire [31:0] up_wdata_s;
up/constr: independent read/write and local constraints
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wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
initial checkin
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wire [31:0] up_rdata_s;
up/constr: independent read/write and local constraints
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wire up_rack_s;
initial checkin
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wire hdmi_csc_bypass_s;
axi_hdmi_tx: Add control to bypass chroma sub-sampler Add a control bit to the register map that allows to bypass the chroma sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used to send the test-pattern directly to the HDMI transmitter without modifying it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 19:11:58 +00:00
wire hdmi_ss_bypass_s;
initial checkin
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wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
axi_hdmi_tx: Fixed data bus width
2016-05-05 10:26:59 +00:00
wire [23:0] hdmi_clip_max_s;
wire [23:0] hdmi_clip_min_s;
initial checkin
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wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
a5soc: removed jtag master control
2014-07-01 16:27:37 +00:00
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
initial checkin
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// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// axi interface
Remove BASEADDR/HIGHADDR parameters This is unused and unneeded. The AXI interconnect will make sure that a peripheral only gets requests that are meant for it, there is no need to check the address in the peripheral itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 08:08:10 +00:00
up_axi i_up_axi (
initial checkin
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.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
up/constr: independent read/write and local constraints
2014-10-02 18:35:06 +00:00
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
initial checkin
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.up_wdata (up_wdata_s),
up/constr: independent read/write and local constraints
2014-10-02 18:35:06 +00:00
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
initial checkin
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.up_rdata (up_rdata_s),
up/constr: independent read/write and local constraints
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.up_rack (up_rack_s));
initial checkin
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// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
axi_hdmi_tx: Add control to bypass chroma sub-sampler Add a control bit to the register map that allows to bypass the chroma sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used to send the test-pattern directly to the HDMI transmitter without modifying it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 19:11:58 +00:00
.hdmi_ss_bypass (hdmi_ss_bypass_s),
initial checkin
2014-02-28 19:26:22 +00:00
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
axi_hdmi_tx: Upgrade hdmi clipping process -added two registers that control the clipping ranges (0x01a and 0x01b) -extend clipping process for all output data formats
2016-04-12 19:01:07 +00:00
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s),
initial checkin
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.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
up/constr: independent read/write and local constraints
2014-10-02 18:35:06 +00:00
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
initial checkin
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.up_wdata (up_wdata_s),
up/constr: independent read/write and local constraints
2014-10-02 18:35:06 +00:00
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
initial checkin
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.up_rdata (up_rdata_s),
up/constr: independent read/write and local constraints
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.up_rack (up_rack_s));
initial checkin
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// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
axi_hdmi_tx- altera ip changes
2015-08-27 20:03:03 +00:00
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
axi_hdmi_tx: Update to use ADI DMA The frame synchronization between axi_hdmi_tx and axi_dmac is based on the DMA(2D streaming) last signal. The last signal will be used as an end of frame signal marking the beginning of the future frame to be transferred by the DMA. Only after both HDMI and DMA are ready for a "new frame" data will be requested from the DMA. The datarate and CDC between the axi_dmac and axi_hdmi_tx cores will be handled by axi_hdmi_tx's DMA interface based on a backpressure mechanism.
2018-05-11 15:00:15 +00:00
.vdma_end_of_frame (vdma_end_of_frame),
initial checkin
2014-02-28 19:26:22 +00:00
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
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.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
initial checkin
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i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
axi_hdmi_tx: Add control to bypass chroma sub-sampler Add a control bit to the register map that allows to bypass the chroma sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used to send the test-pattern directly to the HDMI transmitter without modifying it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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.hdmi_ss_bypass (hdmi_ss_bypass_s),
initial checkin
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.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
axi_hdmi_tx: Upgrade hdmi clipping process -added two registers that control the clipping ranges (0x01a and 0x01b) -extend clipping process for all output data formats
2016-04-12 19:01:07 +00:00
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s));
initial checkin
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// hdmi output clock
kcu105: base complete with ethernet errors
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generate
axi_hdmi_tx: Add UltraScale+ architecture to Verilog
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if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE || FPGA_TECHNOLOGY == XILINX_ULTRASCALE_PLUS) begin
kcu105: base complete with ethernet errors
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ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
axi_hdmi_tx: Add parameter to configure the output clock polarity In order to maximize the window where it is safe to capture data we ideally want to launch data on the opposite edge to which it is captured. Since the edge on which data is captured depends on the connected device add a parameter that allows to configure the launching edge. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
kcu105: base complete with ethernet errors
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.C (hdmi_clk),
.Q (hdmi_out_clk));
end
axi_hdmi_tx: Update parameter name
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if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin
library: ported hdmi tx to altera
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altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.outclocken (1'b1),
axi_hdmi_tx: Add parameter to configure the output clock polarity In order to maximize the window where it is safe to capture data we ideally want to launch data on the opposite edge to which it is captured. Since the edge on which data is captured depends on the connected device add a parameter that allows to configure the launching edge. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 09:36:49 +00:00
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
library: ported hdmi tx to altera
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.outclock (hdmi_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
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if (FPGA_TECHNOLOGY == XILINX_7SERIES) begin
initial checkin
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ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
axi_hdmi_tx: Add parameter to configure the output clock polarity In order to maximize the window where it is safe to capture data we ideally want to launch data on the opposite edge to which it is captured. Since the edge on which data is captured depends on the connected device add a parameter that allows to configure the launching edge. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 09:36:49 +00:00
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
initial checkin
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.C (hdmi_clk),
.Q (hdmi_out_clk));
kcu105: base complete with ethernet errors
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end
endgenerate
initial checkin
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endmodule
// ***************************************************************************
// ***************************************************************************