2014-04-07 17:01:10 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9671 (
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_data,
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// dma interface
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adc_clk,
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2014-07-31 19:19:45 +00:00
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adc_valid,
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adc_enable,
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adc_data,
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2014-04-07 17:01:10 +00:00
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adc_dovf,
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adc_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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2014-07-31 19:19:45 +00:00
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s_axi_rready);
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2014-04-07 17:01:10 +00:00
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parameter PCORE_ID = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_4L_2L_N = 1;
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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2014-07-31 19:19:45 +00:00
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parameter C_HIGHADDR = 32'hffffffff;
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parameter C_BASEADDR = 32'h00000000;
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2014-04-07 17:01:10 +00:00
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// jesd interface
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// rx_clk is the jesd clock (ref_clk/2)
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input rx_clk;
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input [(64*PCORE_4L_2L_N)+63:0] rx_data;
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// dma interface
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output adc_clk;
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2014-07-31 19:19:45 +00:00
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output [ 7:0] adc_valid;
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output [ 7:0] adc_enable;
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output [127:0] adc_data;
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2014-04-07 17:01:10 +00:00
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input adc_dovf;
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input adc_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [ 31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [ 31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [ 31:0] s_axi_rdata;
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input s_axi_rready;
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// internal registers
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2014-07-31 19:19:45 +00:00
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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2014-04-07 17:01:10 +00:00
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reg [ 31:0] up_rdata = 'd0;
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2014-07-31 19:19:45 +00:00
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reg up_ack = 'd0;
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2014-04-07 17:01:10 +00:00
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire adc_status_s;
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wire adc_valid_s;
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wire [ 15:0] adc_data_s[7:0];
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wire [ 7:0] adc_or_s;
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wire [ 7:0] up_adc_pn_err_s;
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wire [ 7:0] up_adc_pn_oos_s;
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wire [ 7:0] up_adc_or_s;
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wire up_sel_s;
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wire up_wr_s;
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wire [ 13:0] up_addr_s;
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wire [ 31:0] up_wdata_s;
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2014-07-31 19:19:45 +00:00
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wire [ 31:0] up_rdata_s[8:0];
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wire up_ack_s[8:0];
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2014-04-07 17:01:10 +00:00
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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2014-07-31 19:19:45 +00:00
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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2014-04-07 17:01:10 +00:00
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up_rdata <= 'd0;
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2014-07-31 19:19:45 +00:00
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up_ack <= 'd0;
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2014-04-07 17:01:10 +00:00
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end else begin
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2014-07-31 19:19:45 +00:00
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] |
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up_rdata_s[4] | up_rdata_s[5] | up_rdata_s[6] | up_rdata_s[7] | up_rdata_s[8];
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up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] |
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up_ack_s[4] | up_ack_s[5] | up_ack_s[6] | up_ack_s[7] | up_ack_s[8];
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2014-04-07 17:01:10 +00:00
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end
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end
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// main (device interface)
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axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N)) i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid_s),
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.adc_data_a (adc_data_s[0]),
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.adc_or_a (adc_or_s[0]),
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.adc_data_b (adc_data_s[1]),
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.adc_or_b (adc_or_s[1]),
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.adc_data_c (adc_data_s[2]),
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.adc_or_c (adc_or_s[2]),
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.adc_data_d (adc_data_s[3]),
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.adc_or_d (adc_or_s[3]),
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.adc_data_e (adc_data_s[4]),
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.adc_or_e (adc_or_s[4]),
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.adc_data_f (adc_data_s[5]),
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.adc_or_f (adc_or_s[5]),
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.adc_data_g (adc_data_s[6]),
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.adc_or_g (adc_or_s[6]),
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.adc_data_h (adc_data_s[7]),
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.adc_or_h (adc_or_s[7]),
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.adc_status (adc_status_s));
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// channels
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_channel
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axi_ad9671_channel #(.CHID(n)) i_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s[n]),
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.adc_or (adc_or_s[n]),
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2014-07-31 19:19:45 +00:00
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.adc_dfmt_valid (adc_valid[n]),
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.adc_dfmt_data (adc_data[(n*16)+15:(n*16)]),
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.adc_enable (adc_enable[n]),
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2014-04-07 17:01:10 +00:00
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.up_adc_pn_err (up_adc_pn_err_s[n]),
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.up_adc_pn_oos (up_adc_pn_oos_s[n]),
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.up_adc_or (up_adc_or_s[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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2014-07-31 19:19:45 +00:00
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.up_rdata (up_rdata_s[n]),
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.up_ack (up_ack_s[n]));
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2014-04-07 17:01:10 +00:00
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end
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endgenerate
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// common processor control
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up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd1),
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2014-07-31 19:19:45 +00:00
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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2014-04-07 17:01:10 +00:00
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.delay_clk (1'b0),
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.delay_rst (),
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.delay_sel (),
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.delay_rwn (),
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.delay_addr (),
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.delay_wdata (),
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.delay_rdata (5'd0),
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.delay_ack_t (1'b0),
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2014-04-23 20:39:28 +00:00
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.delay_locked (1'b1),
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2014-04-07 17:01:10 +00:00
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.drp_clk (1'd0),
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.drp_rst (),
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.drp_sel (),
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.drp_wr (),
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.drp_addr (),
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.drp_wdata (),
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.drp_rdata (16'd0),
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.drp_ready (1'd0),
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2014-04-23 20:39:28 +00:00
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.drp_locked (1'd1),
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2014-04-07 17:01:10 +00:00
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.up_usr_chanmax (),
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.adc_usr_chanmax (8'd7),
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2014-07-31 19:19:45 +00:00
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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2014-04-07 17:01:10 +00:00
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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2014-07-31 19:19:45 +00:00
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.up_rdata (up_rdata_s[8]),
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.up_ack (up_ack_s[8]));
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2014-04-07 17:01:10 +00:00
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// up bus interface
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up_axi #(
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.PCORE_BASEADDR (C_BASEADDR),
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.PCORE_HIGHADDR (C_HIGHADDR))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata),
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|
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.up_ack (up_ack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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