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pluto_hdl_adi/projects/fmcomms2/zc702/system_project.tcl

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Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
fmcomms2: Updated project
2015-03-13 10:49:17 +00:00
source $ad_hdl_dir/projects/scripts/adi_board.tcl
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 09:06:50 +00:00
adi_project_xilinx fmcomms2_zc702
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
adi_project_files fmcomms2_zc702 [list \
"system_top.v" \
fmcomms2/zc702- pmod1 udc, pmod2 gpio
2017-08-09 18:08:47 +00:00
"system_constr.xdc" \
lib_refactoring: Fix path of the IO macros
2016-08-05 15:00:34 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
fmcomms2/zc702- pmod1 udc, pmod2 gpio
2017-08-09 18:08:47 +00:00
"$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
adi_project_run fmcomms2_zc702
move/rename - delay script belongs to ad9361
2017-03-10 17:44:32 +00:00
source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00