pluto_hdl_adi/library/util_adcfifo/util_adcfifo_hw.tcl



package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl

ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
ad_ip_files util_adcfifo [list\
  $ad_hdl_dir/library/altera/common/ad_mem_asym.v \
  $ad_hdl_dir/library/common/ad_axis_inf_rx.v \
  util_adcfifo.v \
  util_adcfifo_constr.sdc]

# parameters

ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
ad_ip_parameter DMA_READY_ENABLE INTEGER 1
ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10

# interfaces

ad_alt_intf clock adc_clk input 1 adc_clk
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_wr input 1 valid
ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
ad_alt_intf signal adc_wovf output 1 ovf

ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf signal dma_wr output 1 valid
ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
ad_alt_intf signal dma_wready input 1 ready
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_status output 4 xfer_status
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00

altera- default to latest version 2017-05-12 17:25:17 +00:00			`package require qsys`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00			`source ../scripts/adi_env.tcl`
			`source ../scripts/adi_ip_alt.tcl`

adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}`
			`ad_ip_files util_adcfifo [list\`
adcfifo- asym_mem primitive changes 2017-03-01 20:55:56 +00:00			`$ad_hdl_dir/library/altera/common/ad_mem_asym.v \`
adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`$ad_hdl_dir/library/common/ad_axis_inf_rx.v \`
			`util_adcfifo.v \`
			`util_adcfifo_constr.sdc]`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00
			`# parameters`

adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}`
			`ad_ip_parameter ADC_DATA_WIDTH INTEGER 256`
			`ad_ip_parameter DMA_DATA_WIDTH INTEGER 64`
			`ad_ip_parameter DMA_READY_ENABLE INTEGER 1`
			`ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00
adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`# interfaces`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00
adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`ad_alt_intf clock adc_clk input 1 adc_clk`
			`ad_alt_intf reset adc_rst input 1 if_adc_clk`
			`ad_alt_intf signal adc_wr input 1 valid`
			`ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data`
			`ad_alt_intf signal adc_wovf output 1 ovf`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00
adc/dac-fifo altera cores 2017-02-28 18:30:50 +00:00			`ad_alt_intf clock dma_clk input 1 clk`
			`ad_alt_intf signal dma_wr output 1 valid`
			`ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data`
			`ad_alt_intf signal dma_wready input 1 ready`
			`ad_alt_intf signal dma_xfer_req input 1 xfer_req`
			`ad_alt_intf signal dma_xfer_status output 4 xfer_status`
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component 2015-11-04 11:31:50 +00:00