261 lines
8.4 KiB
ReStructuredText
261 lines
8.4 KiB
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.. _adaq7980_sdz:
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ADAQ7980-SDZ HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`ADAQ7980`/:adi:`ADAQ7988` are 16-bit analog-to-digital converter
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(ADC) subsystems that integrate four common signal processing and conditioning
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blocks into a system in package (SiP) design that supports a variety of
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applications. These devices contain the most critical passive components,
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eliminating many of the design challenges associated with traditional signal
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chains that use successive approximation register (SAR) ADCs. These passive
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components are crucial to achieving the specified device performance.
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The :adi:`ADAQ7980`/:adi:`ADAQ7988` contain a high accuracy, low power,
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16-bit SAR ADC, a low power, high bandwidth, high input impedance ADC driver,
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a low power, stable reference buffer, and an efficient power management block.
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Housed within a tiny, 5 mm × 4 mm LGA package, these systems simplify the
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design process for data acquisition systems. The level of system integration
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of the :adi:`ADAQ7980`/:adi:`ADAQ7988` solves many design challenges, while
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the devices still provide the flexibility of a configurable ADC driver feedback
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loop to allow gain and/or common-mode adjustments. A set of four device
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supplies provides optimal system performance; however, single-supply operation
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is possible with minimal impact on device operating specifications.
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Using the SDI input, the SPI-compatible serial interface features the ability
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to daisy-chain multiple devices on a single, 3-wire bus and provides an optional
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busy indicator. The user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V
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logic. Specified operation of these devices is from −55°C to +125°C.
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Applications:
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* Automated test equipment (ATE)
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* Battery powered instrumentation
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* Communications
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* Data acquisition
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* Process control
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* Medical instruments
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-ADAQ7980 <EVAL-ADAQ7980>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`ADAQ7980`
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- :adi:`ADAQ7988`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. image:: adaq7980_sdz_hdl.svg
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:width: 800
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:align: center
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:alt: ADAQ7980_SDZ block diagram
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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=========================== ==========
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Instance Address
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=========================== ==========
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axi_adaq7980_dma 0x44a30000
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spi_clkgen 0x44a70000
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spi_adaq7980_adc_axi_regmap 0x44a00000
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spi_trigger_gen 0x44b00000
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=========================== ==========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* - PL
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- iic_fmc
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- axi_iic_fmc
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- 0x4162_0000
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- ---
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* - PL
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- iic_main
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- axi_iic_main
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- 0x4160_0000
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- ---
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PL
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- axi_spi_engine
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- adaq7980
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - adaq7980_rbuf_pf
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- INOUT
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- 41
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- 95
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* - adaq7980_ref_pd
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- INOUT
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- 40
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- 94
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* - adaq7980_gpio
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- INOUT
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- 39:32
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- 93:86
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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================ === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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================ === ========== ===========
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axi_adaq7980_dma 13 57 89
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spi_adaq7980 12 56 88
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================ === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get the source
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you must `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/adaq7980_sdz/zed
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user@analog:~/hdl/projects/adaq7980_sdz/zed$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :dokuwiki:`ADAQ7980 User guide <resources/eval/user-guides/adaq7980-sdz>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheet: :adi:`ADAQ7980`/:adi:`ADAQ7988`
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- `UG-1060, Evaluation Board User Guide <https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7980-7988.pdf>`__
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`adaq7980_sdz HDL project <projects/adaq7980_sdz>`
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- :ref:`SPI_ENGINE <spi_engine>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_dmac <main:library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <master:library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <main:library/axi_hdmi_tx>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi <main:library/axi_i2s_adi>`
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- ---
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen <main:library/axi_pwm_gen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx <main:library/axi_spdif_tx>`
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- ---
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* - AXI_SPI_ENGINE
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- :git-hdl:`library/spi_engine/axi_spi_engine <main:library/spi_engine/axi_spi_engine>`
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- :ref:`here <spi_engine axi>`
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid <main:library/axi_sysid>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - SPI_ENGINE_EXECUTION
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- :git-hdl:`library/spi_engine/spi_engine_execution <main:library/spi_engine/spi_engine_execution>`
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- :ref:`here <spi_engine execution>`
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* - SPI_ENGINE_INTERCONNECT
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- :git-hdl:`library/spi_engine/spi_engine_interconnect <main:library/spi_engine/spi_engine_interconnect>`
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- :ref:`here <spi_engine interconnect>`
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* - SPI_ENGINE_OFFLOAD
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- :git-hdl:`library/spi_engine/spi_engine_offload <main:library/spi_engine/spi_engine_offload>`
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- :ref:`here <spi_engine offload>`
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* - SYSID_ROM
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- :git-hdl:`library/sysid_rom <main:library/sysid_rom>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_I2C_MIXER
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- :git-hdl:`library/util_i2c_mixer <main:library/util_i2c_mixer>`
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- :ref:`here <spi_engine offload>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-no-os:`No-OS project <projects/adaq7980_sdz>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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