2014-12-08 15:44:15 +00:00
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
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2017-02-22 20:56:37 +00:00
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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2014-12-08 15:44:15 +00:00
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source ../common/fmcadc5_bd.tcl
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2015-10-29 20:48:21 +00:00
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# ila
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2014-12-08 15:44:15 +00:00
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2015-10-29 20:48:21 +00:00
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set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc
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2015-11-02 17:10:08 +00:00
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set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc
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2015-10-29 20:48:21 +00:00
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2016-08-30 13:09:28 +00:00
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
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2015-10-29 20:48:21 +00:00
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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2015-11-02 17:10:08 +00:00
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
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2015-10-29 20:48:21 +00:00
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
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2016-11-23 21:21:57 +00:00
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
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ad_connect util_ad9625_cpack/adc_valid mfifo_adc/din_valid
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ad_connect util_ad9625_cpack/adc_data mfifo_adc/din_data_0
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk
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2015-10-29 20:48:21 +00:00
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ad_connect mfifo_adc/dout_valid ila_adc/probe0
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ad_connect mfifo_adc/dout_data_0 ila_adc/probe1
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2015-11-02 17:10:08 +00:00
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