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pluto_hdl_adi/library/axi_ad5766/axi_ad5766_ip.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
# ip
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
global VIVADO_IP_LIBRARY
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
adi_ip_create axi_ad5766
adi_ip_files axi_ad5766 [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
"up_ad5766_sequencer.v" \
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
"axi_ad5766.v" ]
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
adi_ip_properties axi_ad5766
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
adi_init_bd_tcl
library/IPs: Auto-generate bd.tcl Update Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to auto-generate bd.tcl for: - axi_ad5766/axi_ad5766_ip.tcl - axi_ad6676/axi_ad6676_ip.tcl - axi_ad9122/axi_ad9122_ip.tcl - axi_ad9144/axi_ad9144_ip.tcl - axi_ad9152/axi_ad9152_ip.tcl - axi_ad9162/axi_ad9162_ip.tcl - axi_ad9250/axi_ad9250_ip.tcl - axi_ad9265/axi_ad9265_ip.tcl - axi_ad9361/axi_ad9361_ip.tcl - axi_ad9371/axi_ad9371_ip.tcl - axi_ad9434/axi_ad9434_ip.tcl - axi_ad9467/axi_ad9467_ip.tcl - axi_ad9625/axi_ad9625_ip.tcl - axi_ad9671/axi_ad9671_ip.tcl - axi_ad9680/axi_ad9680_ip.tcl - axi_ad9684/axi_ad9684_ip.tcl - axi_ad9739a/axi_ad9739a_ip.tcl - axi_ad9963/axi_ad9963_ip.tcl - axi_adrv9009/axi_adrv9009_ip.tcl - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl - axi_hdmi_tx/axi_hdmi_tx_ip.tcl - xilinx/axi_adxcvr/Makefile - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl - xilinx/util_adxcvr/Makefile - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-14 15:25:36 +00:00
adi_ip_bd axi_ad5766 "bd/bd.tcl"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
Create CDC helper library Move the CDC helper modules to a dedicated helper modules. This makes it possible to reference them without having to use file paths that go outside of the referencing project's directory. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-18 13:12:01 +00:00
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd_data" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
}
adi_add_bus "spi_engine_offload_ctrl" "slave" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
{ "ctrl_enable" "ENABLE"} \
{ "ctrl_enabled" "ENABLED"} \
{ "ctrl_mem_reset" "MEM_RESET"} \
}
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
adi_add_bus_clock "dma_clk" "dma_fifo_tx"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
axi_ad5766: Initial commit This core can be used in conjunction with the SPI_ENGINE, will work as an offload module, forwarding a data stream to the SPI excecution, received from a DMA.
2016-10-28 07:32:30 +00:00
ipx::save_core [ipx::current_core]