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pluto_hdl_adi/library/axi_ad9625/axi_ad9625_ip.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9625
adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
ad9625- xcvr updates
2016-09-26 19:21:11 +00:00
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
library: Update scripts with new constraints Update all IPs tcl scripts with the new constraints files. Refer to commit 335fef0.
2017-03-30 13:12:07 +00:00
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \
"axi_ad9625_if.v" \
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
"axi_ad9625.v" ]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_properties axi_ad9625
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
adi_init_bd_tcl
library/IPs: Auto-generate bd.tcl Update Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to auto-generate bd.tcl for: - axi_ad5766/axi_ad5766_ip.tcl - axi_ad6676/axi_ad6676_ip.tcl - axi_ad9122/axi_ad9122_ip.tcl - axi_ad9144/axi_ad9144_ip.tcl - axi_ad9152/axi_ad9152_ip.tcl - axi_ad9162/axi_ad9162_ip.tcl - axi_ad9250/axi_ad9250_ip.tcl - axi_ad9265/axi_ad9265_ip.tcl - axi_ad9361/axi_ad9361_ip.tcl - axi_ad9371/axi_ad9371_ip.tcl - axi_ad9434/axi_ad9434_ip.tcl - axi_ad9467/axi_ad9467_ip.tcl - axi_ad9625/axi_ad9625_ip.tcl - axi_ad9671/axi_ad9671_ip.tcl - axi_ad9680/axi_ad9680_ip.tcl - axi_ad9684/axi_ad9684_ip.tcl - axi_ad9739a/axi_ad9739a_ip.tcl - axi_ad9963/axi_ad9963_ip.tcl - axi_adrv9009/axi_adrv9009_ip.tcl - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl - axi_hdmi_tx/axi_hdmi_tx_ip.tcl - xilinx/axi_adxcvr/Makefile - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl - xilinx/util_adxcvr/Makefile - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-14 15:25:36 +00:00
adi_ip_bd axi_ad9122 "bd/bd.tcl"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
ad9625- xcvr updates
2016-09-26 19:21:11 +00:00
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ipx::save_core [ipx::current_core]