2016-06-17 15:59:42 +00:00
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## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
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2016-06-16 20:41:43 +00:00
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2016-08-04 17:28:25 +00:00
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source ../../scripts/adi_env.tcl
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2016-06-16 20:41:43 +00:00
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create util_adxcvr
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adi_ip_files util_adxcvr [list \
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2019-01-11 08:54:16 +00:00
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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2016-07-15 14:19:48 +00:00
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"util_adxcvr_constr.xdc" \
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2016-06-17 15:59:42 +00:00
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"util_adxcvr_xcm.v" \
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"util_adxcvr_xch.v" \
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2019-04-02 08:18:25 +00:00
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"util_adxcvr.v" ]
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2016-06-16 20:41:43 +00:00
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adi_ip_properties_lite util_adxcvr
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2019-04-02 08:18:25 +00:00
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adi_init_bd_tcl
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2019-03-14 15:25:36 +00:00
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adi_ip_bd util_adxcvr "bd/bd.tcl"
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2019-01-11 08:54:16 +00:00
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2016-06-17 15:59:42 +00:00
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ipx::remove_all_bus_interface [ipx::current_core]
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2018-02-15 08:41:14 +00:00
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ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface cpll_ref_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface qpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface qpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface qpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface qpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface rx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_rx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface up_tx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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2016-06-17 15:59:42 +00:00
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set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
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for {set n 0} {$n < 16} {incr n} {
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if {($n%4) == 0} {
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2017-05-22 14:41:58 +00:00
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adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \
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2016-06-17 15:59:42 +00:00
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"enb up_cm_enb_${n} "\
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"addr up_cm_addr_${n} "\
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"wr up_cm_wr_${n} "\
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"wdata up_cm_wdata_${n} "\
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"rdata up_cm_rdata_${n} "\
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"ready up_cm_ready_${n} "]
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}
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2017-05-22 14:41:58 +00:00
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adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \
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2016-06-17 15:59:42 +00:00
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"enb up_es_enb_${n} "\
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"addr up_es_addr_${n} "\
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"wr up_es_wr_${n} "\
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"wdata up_es_wdata_${n} "\
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"rdata up_es_rdata_${n} "\
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2018-11-08 13:54:15 +00:00
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"reset up_es_reset_${n} "\
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2016-06-17 15:59:42 +00:00
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"ready up_es_ready_${n} "]
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2017-05-22 14:41:58 +00:00
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adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \
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2016-06-17 15:59:42 +00:00
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"pll_locked up_rx_pll_locked_${n} "\
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"rst up_rx_rst_${n} "\
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|
|
|
|
"user_ready up_rx_user_ready_${n} "\
|
|
|
|
|
"rst_done up_rx_rst_done_${n} "\
|
|
|
|
|
"lpm_dfe_n up_rx_lpm_dfe_n_${n} "\
|
|
|
|
|
"rate up_rx_rate_${n} "\
|
|
|
|
|
"sys_clk_sel up_rx_sys_clk_sel_${n} "\
|
|
|
|
|
"out_clk_sel up_rx_out_clk_sel_${n} "\
|
|
|
|
|
"enb up_rx_enb_${n} "\
|
|
|
|
|
"addr up_rx_addr_${n} "\
|
|
|
|
|
"wr up_rx_wr_${n} "\
|
|
|
|
|
"wdata up_rx_wdata_${n} "\
|
|
|
|
|
"rdata up_rx_rdata_${n} "\
|
|
|
|
|
"ready up_rx_ready_${n} "]
|
|
|
|
|
|
2017-05-22 14:41:58 +00:00
|
|
|
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \
|
2016-06-17 15:59:42 +00:00
|
|
|
"pll_locked up_tx_pll_locked_${n} "\
|
|
|
|
|
"rst up_tx_rst_${n} "\
|
|
|
|
|
"user_ready up_tx_user_ready_${n} "\
|
|
|
|
|
"rst_done up_tx_rst_done_${n} "\
|
|
|
|
|
"lpm_dfe_n up_tx_lpm_dfe_n_${n} "\
|
|
|
|
|
"rate up_tx_rate_${n} "\
|
|
|
|
|
"sys_clk_sel up_tx_sys_clk_sel_${n} "\
|
|
|
|
|
"out_clk_sel up_tx_out_clk_sel_${n} "\
|
2018-10-01 15:36:39 +00:00
|
|
|
"tx_diffctrl up_tx_diffctrl_${n} "\
|
|
|
|
|
"tx_postcursor up_tx_postcursor_${n} "\
|
|
|
|
|
"tx_precursor up_tx_precursor_${n} "\
|
2016-06-17 15:59:42 +00:00
|
|
|
"enb up_tx_enb_${n} "\
|
|
|
|
|
"addr up_tx_addr_${n} "\
|
|
|
|
|
"wr up_tx_wr_${n} "\
|
|
|
|
|
"wdata up_tx_wdata_${n} "\
|
|
|
|
|
"rdata up_tx_rdata_${n} "\
|
|
|
|
|
"ready up_tx_ready_${n} "]
|
|
|
|
|
|
|
|
|
|
ipx::add_bus_interface rx_${n} [ipx::current_core]
|
|
|
|
|
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
|
|
|
|
|
ipx::add_bus_interface tx_${n} [ipx::current_core]
|
|
|
|
|
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \
|
|
|
|
|
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \
|
|
|
|
|
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
|
|
|
|
|
set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \
|
|
|
|
|
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_ports rx_*0* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*0* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
|
|
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_ports rx_*1* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*1* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_ports rx_*2* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*2* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_ports rx_*3* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*3* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_ports rx_*4* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*4* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 16:21:04 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
|
|
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_ports rx_*5* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*5* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_ports rx_*6* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*6* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_ports rx_*7* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*7* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_ports rx_*8* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*8* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_ports rx_*9* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*9* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_ports rx_*10* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*10* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_ports rx_*11* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*11* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_ports rx_*12* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*12* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency \
|
2016-11-22 16:21:04 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
|
|
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_ports rx_*13* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*13* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_ports rx_*14* -of_objects [ipx::current_core]]
|
|
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*14* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
|
|
|
|
[ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \
|
|
|
|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
|
2016-11-22 19:43:36 +00:00
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[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
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2017-04-06 09:36:47 +00:00
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|
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[ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]]
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2016-06-17 15:59:42 +00:00
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
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[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
|
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|
|
|
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|
|
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
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|
|
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[ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]]
|
|
|
|
|
|
|
|
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
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[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
|
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|
|
|
|
|
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|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
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[ipx::get_ports rx_*15* -of_objects [ipx::current_core]]
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|
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2018-03-06 13:46:49 +00:00
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
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[ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \
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|
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2016-06-17 15:59:42 +00:00
|
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
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[ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]]
|
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|
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|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
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[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
|
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|
|
|
|
|
|
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports tx_*15* -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2018-03-06 13:46:49 +00:00
|
|
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
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|
|
|
[ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \
|
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|
|
|
2016-06-17 15:59:42 +00:00
|
|
|
set_property enablement_dependency \
|
2016-11-22 15:33:40 +00:00
|
|
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
|
2016-11-22 16:21:04 +00:00
|
|
|
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
|
2016-11-22 19:43:36 +00:00
|
|
|
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
|
2017-04-06 09:36:47 +00:00
|
|
|
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
|
2016-06-17 15:59:42 +00:00
|
|
|
|
2019-01-11 08:54:16 +00:00
|
|
|
adi_add_auto_fpga_spec_params
|
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|
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ipx::create_xgui_files [ipx::current_core]
|
|
|
|
|
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2016-06-16 20:41:43 +00:00
|
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ipx::save_core [ipx::current_core]
|
|
|
|
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|
