2023-08-16 12:57:14 +00:00
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.. _spi_engine control-interface:
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SPI Engine Control Interface
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================================================================================
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The SPI Engine Control Interface is used to exchange data between different
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cores within the SPI Engine framework. It is used to exchange the commands and
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synchronization points as well as the SPI bus transmit and receive data.
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The interface consists of four streams:
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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* The CMD stream which carries the SPI Engine commands. (Manager to Subordinate)
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2023-08-16 12:57:14 +00:00
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* The SDO stream which carries the to be transmitted data for the SPI bus.
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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(Manager to Subordinate)
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* The SDI stream which carries the received data from the SPI bus. (Subordinate to
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Manager)
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* The SYNC stream which carries the synchronization events. (Subordinate to Manager)
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2023-08-16 12:57:14 +00:00
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Each of the streams has a valid, ready and data signal. They follow the
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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handshaking protocol as defined by the AXI standard. Meaning the manager asserts
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valid when the data on the data signal is valid and the subordinate asserts ready
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when it is able to accept new data. If both valid and ready are asserted at the same
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time the data has been transmitted from the manager to the subordinate.
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2023-08-16 12:57:14 +00:00
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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docs: links, drop part, fixups, codeowners
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
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* - :git-hdl:`library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml`
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2023-08-16 12:57:14 +00:00
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- Interface definition file
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Signal Pins
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--------------------------------------------------------------------------------
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.. list-table::
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:widths: 10 10 10 70
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:header-rows: 1
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* - Width
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- Name
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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- Direction (Manager)
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2023-08-16 12:57:14 +00:00
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- Description
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* -
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- ``cmd_ready``
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- Input
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- Ready signal of the CMD stream
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* -
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- ``cmd_valid``
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- Output
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- Valid signal of the CMD stream
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* - [15:0]
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- ``cmd_data``
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- Output
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- Data signal of the CMD stream
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* -
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- ``sdo_ready``
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- Input
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- Ready signal of the SDO stream
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* -
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- ``sdo_valid``
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- Output
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- Valid signal of the SDO stream
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* - [DATA_WIDTH-1:0]
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- ``sdo_data``
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- Output
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- Data signal of the SDO stream
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* -
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- ``sdi_ready``
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- Output
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- Ready signal of the SDI stream
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* -
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- ``sdi_valid``
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- Input
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- Valid signal of the SDI stream
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* - [(NUM_OF_SDI*DATA_WIDTH-1):0]
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- ``sdi_data``
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- Input
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- Data signal of the SDI stream
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* -
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- ``sync_ready``
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- Output
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- Ready signal of the SYNC stream
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* -
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- ``sync_valid``
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- Input
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- Valid signal of the SYNC stream
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* - [7:0]
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- ``sync_data``
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- Input
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- Data signal of the sync stream
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