2017-05-17 08:44:52 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-31 15:15:24 +00:00
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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2018-03-14 14:45:47 +00:00
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// freedoms and responsibilities that he or she has by using this source/core.
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2017-05-31 15:15:24 +00:00
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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2017-05-29 06:55:41 +00:00
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-29 06:55:41 +00:00
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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2015-06-26 09:04:19 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// 1. The GNU General Public License version 2 as published by the
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2017-05-31 15:15:24 +00:00
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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2017-05-31 15:15:24 +00:00
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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2017-05-29 06:55:41 +00:00
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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2017-05-17 08:44:52 +00:00
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module delay_30_degrees
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//----------- Paramters Declarations -------------------------------------------
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_i,
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input [31:0] offset_i, // offset register
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input [2:0] position_i, // input position
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output reg [2:0] position_o // delayed with 30 degrees position
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);
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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localparam MAX_SPEED_COUNT = 32'h1000000;
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//State machine
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localparam RESET = 6'b000001;
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localparam INIT = 6'b000010;
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localparam CHANGE_POSITION = 6'b000100;
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localparam DELAY_30_DEGREES = 6'b001000;
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localparam APPLY_CHANGE = 6'b010000;
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localparam IDLE = 6'b100000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [5:0] state = RESET; // current state
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reg [5:0] next_state = RESET; // next state
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reg [2:0] position_old = 3'h0; // saves the latest position
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reg [31:0] speed_count = 32'h0; // counts the current speed of rotation
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reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees
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reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// State transitions
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always @*
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begin
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next_state = state;
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case (state)
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RESET:
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begin
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next_state = INIT;
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end
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INIT:
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begin
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if (position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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CHANGE_POSITION:
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begin
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next_state = DELAY_30_DEGREES;
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end
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DELAY_30_DEGREES:
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begin
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if( delay_count > speed_divider)
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begin
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next_state = APPLY_CHANGE;
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end
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end
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APPLY_CHANGE:
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begin
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next_state = IDLE;
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end
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IDLE:
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begin
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if (position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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default:
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begin
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next_state = RESET;
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end
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endcase
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end
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always @(posedge clk_i)
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begin
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case(state)
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RESET:
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begin
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speed_count <= 0;
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speed_divider <= 0;
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position_o <= 3'b1;
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end
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INIT:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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CHANGE_POSITION:
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begin
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speed_divider <= speed_count >> 1 ;
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speed_count <= 0;
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delay_count <= 0;
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end
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DELAY_30_DEGREES:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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delay_count <= delay_count + 1;
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end
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APPLY_CHANGE:
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begin
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if (position_i == 3'b101)
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begin
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position_o <= 100;
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end
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if (position_i == 3'b100)
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begin
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position_o <= 110;
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end
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if (position_i == 3'b110)
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begin
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position_o <= 010;
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end
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if (position_i == 3'b010)
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begin
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position_o <= 011;
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end
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if (position_i == 3'b011)
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begin
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position_o <= 001;
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end
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if (position_i == 3'b001)
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begin
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position_o <= 101;
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end
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position_old <= position_i;
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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IDLE:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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endcase
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end
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always @ (posedge clk_i)
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begin
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if(rst_i == 1'b1)
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begin
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state <= RESET;
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end
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else
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begin
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state <= next_state;
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end
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end
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endmodule
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