23 lines
906 B
Plaintext
23 lines
906 B
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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# Asynchronous GPIOs
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foreach async_input {adc_fda adc_fdb clkd_status[*] dac_irq gpio_bd_i[*] trig} {
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set_false_path -from [get_ports $async_input]
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}
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foreach async_output {adc_pd clkd_sync dac_reset dac_txen gpio_bd_o[*]} {
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set_false_path -to [get_ports $async_output]
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}
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# We really only want to constrain the known good reset paths that are properly
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# synchronized here to be able to spot bad paths when they get added.
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set_false_path -from [get_ports sys_resetn] -to [get_registers *altera_reset_synchronizer_int_chain*]
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set_false_path -from [get_ports sys_resetn] -to [get_keepers *altera_emif*]
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derive_pll_clocks
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derive_clock_uncertainty
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