2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2022-07-12 11:06:15 +00:00
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source ../../../scripts/adi_env.tcl
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2021-02-15 08:02:41 +00:00
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value
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#
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# Use over-writable parameters from the environment.
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#
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# e.g.
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2022-09-08 07:48:27 +00:00
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# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4
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# make JESD_MODE=64B66B RX_LANE_RATE=16.22016 TX_LANE_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
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2021-02-15 08:02:41 +00:00
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# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
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#
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# Parameter description:
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# JESD_MODE : Used link layer encoder mode
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# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
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# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
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#
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2022-09-08 07:48:27 +00:00
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# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA )
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# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE )
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2021-02-15 08:02:41 +00:00
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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2022-03-03 07:43:01 +00:00
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# [RX/TX]_JESD_S : Number of samples per frame
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2021-02-15 08:02:41 +00:00
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# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
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# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
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2022-03-03 07:43:01 +00:00
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# [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M)
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2021-02-15 08:02:41 +00:00
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#
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adi_project ad9082_fmca_ebz_vcu118 0 [list \
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2022-09-08 07:48:27 +00:00
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JESD_MODE [get_env_param JESD_MODE 8B10B ] \
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RX_LANE_RATE [get_env_param RX_LANE_RATE 15 ] \
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TX_LANE_RATE [get_env_param TX_LANE_RATE 15 ] \
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RX_JESD_M [get_env_param RX_JESD_M 4 ] \
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RX_JESD_L [get_env_param RX_JESD_L 8 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
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RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 4 ] \
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TX_JESD_L [get_env_param TX_JESD_L 8 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
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TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
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2021-05-05 11:47:13 +00:00
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RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \
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TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \
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2021-02-15 08:02:41 +00:00
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]
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adi_project_files ad9082_fmca_ebz_vcu118 [list \
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"../../ad9081_fmca_ebz/vcu118/system_top.v" \
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"../../ad9081_fmca_ebz/vcu118/system_constr.xdc"\
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"../../ad9081_fmca_ebz/vcu118/timing_constr.xdc"\
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"../../../library/common/ad_3w_spi.v"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
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2021-06-03 11:39:31 +00:00
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# Avoid critical warning in OOC mode from the clock definitions
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# since at that stage the submodules are not stiched together yet
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if {$ADI_USE_OOC_SYNTHESIS == 1} {
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set_property used_in_synthesis false [get_files timing_constr.xdc]
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}
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2021-02-15 08:02:41 +00:00
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adi_project_run ad9082_fmca_ebz_vcu118
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