2015-08-14 15:24:27 +00:00
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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2016-06-17 16:00:15 +00:00
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adi_if_define if_xcvr_cm
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adi_if_ports output 1 enb
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adi_if_ports output 12 addr
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adi_if_ports output 1 wr
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adi_if_ports output 16 wdata
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adi_if_ports input 16 rdata
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adi_if_ports input 1 ready
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adi_if_define if_xcvr_ch
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adi_if_ports input 1 pll_locked
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adi_if_ports output 1 rst
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adi_if_ports output 1 user_ready
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adi_if_ports input 1 rst_done
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adi_if_ports output 1 lpm_dfe_n
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adi_if_ports output 3 rate
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adi_if_ports output 2 sys_clk_sel
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adi_if_ports output 3 out_clk_sel
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adi_if_ports output 1 enb
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adi_if_ports output 12 addr
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adi_if_ports output 1 wr
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adi_if_ports output 16 wdata
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adi_if_ports input 16 rdata
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adi_if_ports input 1 ready
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2015-08-14 19:33:36 +00:00
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adi_if_define if_gt_qpll
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adi_if_ports output 1 qpll_rst reset
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adi_if_ports output 1 qpll_ref_clk clock
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2015-08-14 15:24:27 +00:00
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2015-08-14 19:33:36 +00:00
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adi_if_define if_gt_pll
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adi_if_ports output 1 cpll_rst_m reset
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adi_if_ports output 1 cpll_ref_clk_in clock
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2015-08-14 15:24:27 +00:00
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2015-08-14 19:33:36 +00:00
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adi_if_define if_gt_rx
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2015-08-14 15:24:27 +00:00
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adi_if_ports output 1 rx_p
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adi_if_ports output 1 rx_n
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adi_if_ports input 1 rx_rst reset
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adi_if_ports output 1 rx_rst_m reset
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2015-10-02 16:53:23 +00:00
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adi_if_ports input 1 rx_pll_rst reset
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2015-08-14 15:24:27 +00:00
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adi_if_ports input 1 rx_gt_rst reset
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adi_if_ports output 1 rx_gt_rst_m reset
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adi_if_ports input 1 rx_pll_locked
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adi_if_ports output 1 rx_pll_locked_m
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adi_if_ports input 1 rx_user_ready
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adi_if_ports output 1 rx_user_ready_m
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adi_if_ports input 1 rx_rst_done
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adi_if_ports output 1 rx_rst_done_m
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adi_if_ports input 1 rx_out_clk clock
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adi_if_ports output 1 rx_clk clock
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adi_if_ports output 1 rx_sysref
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adi_if_ports input 1 rx_sync
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adi_if_ports input 1 rx_sof
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adi_if_ports input 32 rx_data
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adi_if_ports input 1 rx_ip_rst reset
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adi_if_ports output 4 rx_ip_sof
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adi_if_ports output 32 rx_ip_data
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adi_if_ports input 1 rx_ip_sysref
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adi_if_ports output 1 rx_ip_sync
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adi_if_ports input 1 rx_ip_rst_done
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2015-08-14 19:33:36 +00:00
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adi_if_define if_gt_tx
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adi_if_ports input 1 tx_p
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adi_if_ports input 1 tx_n
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adi_if_ports input 1 tx_rst reset
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adi_if_ports output 1 tx_rst_m reset
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2015-10-02 16:53:23 +00:00
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adi_if_ports input 1 tx_pll_rst reset
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2015-08-14 19:33:36 +00:00
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adi_if_ports input 1 tx_gt_rst reset
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adi_if_ports output 1 tx_gt_rst_m reset
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adi_if_ports input 1 tx_pll_locked
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adi_if_ports output 1 tx_pll_locked_m
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adi_if_ports input 1 tx_user_ready
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adi_if_ports output 1 tx_user_ready_m
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adi_if_ports input 1 tx_rst_done
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adi_if_ports output 1 tx_rst_done_m
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adi_if_ports input 1 tx_out_clk clock
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adi_if_ports output 1 tx_clk clock
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adi_if_ports output 1 tx_sysref
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adi_if_ports output 1 tx_sync
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adi_if_ports output 32 tx_data
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adi_if_ports input 1 tx_ip_rst reset
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adi_if_ports input 32 tx_ip_data
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adi_if_ports input 1 tx_ip_sysref
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adi_if_ports input 1 tx_ip_sync
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adi_if_ports input 1 tx_ip_rst_done
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adi_if_define if_gt_rx_ksig
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adi_if_ports output 4 rx_gt_ilas_f
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adi_if_ports output 4 rx_gt_ilas_q
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adi_if_ports output 4 rx_gt_ilas_a
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adi_if_ports output 4 rx_gt_ilas_r
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adi_if_ports output 4 rx_gt_cgs_k
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2015-08-14 15:24:27 +00:00
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