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pluto_hdl_adi/library/axi_ad9361/axi_ad9361_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
axi_ad9361: Add CDC constraints Add proper constraints for all the CDC synchronizer paths to the axi_ad9361 core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 15:16:41 +00:00
axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 09:43:10 +00:00
set_property ASYNC_REG TRUE \
[get_cells -hier *enable_up_*] \
[get_cells -hier *txnrx_up_*] \
[get_cells -hier *tdd_sync_d*]
axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only Set the ASYNC_REG property on the bit synchronizer CDC control regs. This hint to Vivado that the registers are used for CDC purposes. Also use -datapath_only for the set_max_delay constraints on the CDC data path to remove the hold time requirement. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:15:10 +00:00
ad9361- ensm through dev-if
2015-08-27 15:14:41 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *up_enable_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *enable_up_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *txnrx_up_m1_reg && IS_SEQUENTIAL}]
axi_ad9361: Update constraints in case TDD is disabled
2021-02-17 10:00:43 +00:00
set_false_path -quiet -to [get_cells -quiet -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]
axi_ad9361: Add CDC constraints Add proper constraints for all the CDC synchronizer paths to the axi_ad9361 core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 15:16:41 +00:00