pluto_hdl_adi/library/intel/jesd204_phy/jesd204_phy_glue.v

// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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// The user should read each of these license terms, and understand the
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module jesd204_phy_glue #(
  parameter WIDTH = 20,
  parameter CONST_WIDTH = 1,
  parameter NUM_OF_LANES = 1,
  parameter LANE_INVERT = 0
) (
  input [WIDTH-1:0] in,
  output [WIDTH-1:0] out,
  output [CONST_WIDTH-1:0] const_out,
  output [NUM_OF_LANES-1:0] polinv
);

/* There really should be a standard component in Qsys that allows to do this */

  assign out = in;
  assign const_out = {CONST_WIDTH{1'b0}};
  assign polinv = LANE_INVERT[NUM_OF_LANES-1:0];

endmodule