67 lines
3.8 KiB
Tcl
67 lines
3.8 KiB
Tcl
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# fifo and controller (read side)
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proc p_sys_rfifo {p_name m_name dac_data_width dma_data_width} {
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global ad_hdl_dir
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set p_instance [get_bd_cells $p_name]
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set c_instance [current_bd_instance .]
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current_bd_instance $p_instance
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set m_instance [create_bd_cell -type hier $m_name]
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current_bd_instance $m_instance
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create_bd_pin -dir I -type clk dac_clk
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create_bd_pin -dir I dac_rd
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create_bd_pin -dir O -from [expr ($dac_data_width-1)] -to 0 dac_rdata
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create_bd_pin -dir O dac_runf
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create_bd_pin -dir I -type clk dma_clk
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create_bd_pin -dir O dma_rd
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create_bd_pin -dir I -from [expr ($dma_data_width-1)] -to 0 dma_rdata
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create_bd_pin -dir I dma_runf
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set rfifo_ctl [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 rfifo_ctl]
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set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $rfifo_ctl
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set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $rfifo_ctl
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set rfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 rfifo_mem]
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set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $rfifo_mem
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set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $rfifo_mem
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set_property -dict [list CONFIG.Input_Data_Width $dma_data_width] $rfifo_mem
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set_property -dict [list CONFIG.Input_Depth {64}] $rfifo_mem
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set_property -dict [list CONFIG.Output_Data_Width $dac_data_width] $rfifo_mem
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set_property -dict [list CONFIG.Underflow_Flag {true}] $rfifo_mem
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set_property -dict [list CONFIG.Reset_Pin {true}] $rfifo_mem
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set_property -dict [list CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant}] $rfifo_mem
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set_property -dict [list CONFIG.Full_Threshold_Assert_Value {50}] $rfifo_mem
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connect_bd_net -net dac_clk [get_bd_pins dac_clk]
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connect_bd_net -net dma_clk [get_bd_pins dma_clk]
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connect_bd_net -net dac_clk [get_bd_pins rfifo_ctl/dac_clk]
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connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/dma_clk]
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connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/wr_clk]
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connect_bd_net -net dac_clk [get_bd_pins rfifo_mem/rd_clk]
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connect_bd_net -net dac_rd [get_bd_pins dac_rd] [get_bd_pins rfifo_ctl/dac_rd]
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connect_bd_net -net dac_rdata [get_bd_pins dac_rdata] [get_bd_pins rfifo_ctl/dac_rdata]
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connect_bd_net -net dac_runf [get_bd_pins dac_runf] [get_bd_pins rfifo_ctl/dac_runf]
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connect_bd_net -net dma_rd [get_bd_pins dma_rd] [get_bd_pins rfifo_ctl/dma_rd]
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connect_bd_net -net dma_rdata [get_bd_pins dma_rdata] [get_bd_pins rfifo_ctl/dma_rdata]
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connect_bd_net -net dma_runf [get_bd_pins dma_runf] [get_bd_pins rfifo_ctl/dma_runf]
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connect_bd_net -net rfifo_ctl_fifo_rst [get_bd_pins rfifo_ctl/fifo_rst] [get_bd_pins rfifo_mem/rst]
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connect_bd_net -net rfifo_ctl_fifo_wr [get_bd_pins rfifo_ctl/fifo_wr] [get_bd_pins rfifo_mem/wr_en]
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connect_bd_net -net rfifo_ctl_fifo_wdata [get_bd_pins rfifo_ctl/fifo_wdata] [get_bd_pins rfifo_mem/din]
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connect_bd_net -net rfifo_ctl_fifo_wfull [get_bd_pins rfifo_ctl/fifo_wfull] [get_bd_pins rfifo_mem/prog_full]
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connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
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connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
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connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
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connect_bd_net -net rfifo_ctl_fifo_runf [get_bd_pins rfifo_ctl/fifo_runf] [get_bd_pins rfifo_mem/underflow]
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current_bd_instance $c_instance
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}
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