2014-04-30 18:40:54 +00:00
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# constraints
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set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
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# uart
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2014-05-06 19:38:44 +00:00
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set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout]
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set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin]
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2014-04-30 18:40:54 +00:00
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2016-08-08 14:53:32 +00:00
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# ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0)
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set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
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2014-07-07 13:53:55 +00:00
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# fan
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2014-04-30 18:40:54 +00:00
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set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
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# sw/led
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2015-03-09 20:05:28 +00:00
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set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]
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set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]
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set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]
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set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]]
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set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]]
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set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]]
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set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[8]]; ## GPIO_DIP_SW0
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set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[9]]; ## GPIO_DIP_SW1
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set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[10]]; ## GPIO_DIP_SW2
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set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[11]]; ## GPIO_DIP_SW3
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set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[12]]; ## GPIO_SW_N
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set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[13]]; ## GPIO_SW_E
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set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[14]]; ## GPIO_SW_S
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set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[15]]; ## GPIO_SW_W
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set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[16]]; ## GPIO_SW_C
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2014-04-30 18:40:54 +00:00
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# iic
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
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2015-08-25 13:12:32 +00:00
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# ddr
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set_property -dict {PACKAGE_PIN AK17} [get_ports sys_clk_p]
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set_property -dict {PACKAGE_PIN AK16} [get_ports sys_clk_n]
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set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44]
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set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45]
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set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
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2016-08-08 14:53:32 +00:00
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create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p]
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set_false_path -to [get_pins -hier -filter {name =~ *ethernet*idelayctrl*/RST}]
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