2016-06-08 15:54:46 +00:00
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# dac peripherals
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2016-09-26 19:19:29 +00:00
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set axi_ad9162_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9162_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9162_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9162_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9162_xcvr
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2016-06-30 17:26:16 +00:00
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set axi_ad9162_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9162:1.0 axi_ad9162_core]
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2016-09-26 19:19:29 +00:00
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set axi_ad9162_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9162_jesd]
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2016-06-30 17:26:16 +00:00
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9162_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9162_jesd
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set axi_ad9162_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9162_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9162_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9162_dma
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set_property -dict [list CONFIG.ID {1}] $axi_ad9162_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9162_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9162_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9162_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9162_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9162_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9162_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9162_dma
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2016-06-08 15:54:46 +00:00
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# adc peripherals
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2016-09-26 19:19:29 +00:00
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set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr
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2016-06-10 18:20:00 +00:00
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set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
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2016-09-26 19:19:29 +00:00
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set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd]
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2016-06-10 18:20:00 +00:00
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
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set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
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2016-06-08 15:54:46 +00:00
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2016-09-26 19:19:29 +00:00
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# shared transceiver core
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2016-06-08 15:54:46 +00:00
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2016-09-26 19:19:29 +00:00
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set util_fmcomms11_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms11_xcvr]
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2016-11-22 21:23:05 +00:00
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set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
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2016-09-26 19:19:29 +00:00
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set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr
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2016-11-22 21:23:05 +00:00
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
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2016-09-26 19:19:29 +00:00
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set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr
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2016-11-22 21:23:05 +00:00
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
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set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
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2016-10-24 13:51:29 +00:00
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set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcomms11_xcvr
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set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10400020}] $util_fmcomms11_xcvr
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2016-06-10 18:20:00 +00:00
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2016-11-22 21:23:05 +00:00
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# reference clocks & resets
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create_bd_port -dir I tx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_*
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2016-09-26 19:19:29 +00:00
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ad_connect sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
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ad_connect sys_cpu_clk util_fmcomms11_xcvr/up_clk
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2016-06-08 15:54:46 +00:00
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# connections (dac)
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2016-09-26 19:19:29 +00:00
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ad_xcvrcon util_fmcomms11_xcvr axi_ad9162_xcvr axi_ad9162_jesd
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ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_core/tx_clk
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ad_connect axi_ad9162_jesd/tx_tdata axi_ad9162_core/tx_data
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ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk
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2016-07-21 15:57:40 +00:00
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ad_connect axi_ad9162_core/dac_valid axi_ad9162_fifo/dac_valid
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ad_connect axi_ad9162_core/dac_ddata axi_ad9162_fifo/dac_data
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2016-06-30 17:26:16 +00:00
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ad_connect sys_cpu_clk axi_ad9162_fifo/dma_clk
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ad_connect sys_cpu_reset axi_ad9162_fifo/dma_rst
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ad_connect sys_cpu_clk axi_ad9162_dma/m_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn
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ad_connect axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req
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ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready
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ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data
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ad_connect axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid
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ad_connect axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
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2016-06-08 15:54:46 +00:00
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# connections (adc)
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2016-09-26 19:19:29 +00:00
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ad_xcvrcon util_fmcomms11_xcvr axi_ad9625_xcvr axi_ad9625_jesd
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ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
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ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
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ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data
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ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
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ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
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2016-06-10 18:20:00 +00:00
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ad_connect axi_ad9625_core/adc_valid axi_ad9625_fifo/adc_wr
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ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
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ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
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ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
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ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
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ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
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ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
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2016-06-08 15:54:46 +00:00
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# interconnect (cpu)
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2016-09-26 19:19:29 +00:00
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ad_cpu_interconnect 0x44A60000 axi_ad9162_xcvr
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2016-06-30 17:26:16 +00:00
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ad_cpu_interconnect 0x44A00000 axi_ad9162_core
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ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9162_dma
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2016-09-26 19:19:29 +00:00
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ad_cpu_interconnect 0x44A50000 axi_ad9625_xcvr
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2016-06-10 18:20:00 +00:00
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ad_cpu_interconnect 0x44A10000 axi_ad9625_core
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ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
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2016-06-08 15:54:46 +00:00
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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2016-09-26 19:19:29 +00:00
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi
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2016-06-08 15:54:46 +00:00
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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2016-06-30 17:26:16 +00:00
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9162_dma/m_src_axi
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2016-06-08 15:54:46 +00:00
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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2016-06-10 18:20:00 +00:00
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
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2016-06-08 15:54:46 +00:00
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# interrupts
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2016-06-30 17:26:16 +00:00
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ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
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2016-06-10 18:20:00 +00:00
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ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
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2016-07-18 12:59:56 +00:00
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# unused
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2017-02-27 20:57:53 +00:00
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ad_connect axi_ad9162_fifo/bypass GND
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2016-07-18 12:59:56 +00:00
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