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Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-17 12:16:18 +00:00
SPDX short identifier: ADIJESD204
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
The ADI JESD204 Core is released under the following license, which is
different than all other HDL cores in this repository.
Please read this, and understand the freedoms and responsibilities you have by
using this source code/core.
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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The JESD204 HDL, is copyright (c) 2016-2023 Analog Devices Inc.
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
This core is free software, you can use run, copy, study, change, ask questions
about and improve this core. Distribution of source, or resulting binaries
(including those inside an FPGA or ASIC) require you to release the source of
the entire project (excluding the system libraries provide by the
tools/compiler/FPGA vendor). These are the terms of the GNU General Public
License version 2 as published by the Free Software Foundation.
This core is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License version 2
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-17 12:16:18 +00:00
along with this source code, and binary. If not, see
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
<http://www.gnu.org/licenses/>.
Commercial licenses (with commercial support) of this JESD204 core are also
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-17 12:16:18 +00:00
available under terms different than the General Public License (e.g. they do
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
not require you to accompany any image (FPGA or ASIC) using the JESD204 core
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-17 12:16:18 +00:00
with any corresponding source code). For these alternate terms you must
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
purchase a license from Analog Devices Technology Licensing Office. Users
interested in such a license should contact jesd204-licensing@analog.com for
more information. This commercial license is sub-licensable (if you purchase
chips from Analog Devices, incorporate them into your PCB level product, and
purchase a JESD204 license, end users of your product will also have a license
to use this core in a commercial setting without releasing their source code).
In addition, we kindly ask you to acknowledge ADI in any program, application
or publication in which you use this JESD204 HDL core. (You are not required to
do so; it is up to your common sense to decide whether you want to comply with
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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this request or not.) For general publications, we suggest referencing: "The
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
design and implementation of the JESD204 HDL Core used in this project is
Add LICENSE_ADIJESD204. Delete jesd204/README.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-17 12:16:18 +00:00
copyright (c) 2016-2023, Analog Devices, Inc."