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pluto_hdl_adi/projects/ad4134_fmc/zed/system_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
# ad4134 SPI configuration interface
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdo] ; ## FMC_LPC_LA04_N
projects/ad4134_fmc: Add FMC pinout descripton * Added txt description of all FMC pins used/unused * Updated constraint files with FMC pinout location Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-09-28 09:47:13 +00:00
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sclk] ; ## FMC_LPC_LA01_P_CC
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_cs] ; ## FMC_LPC_LA05_P
# ad4134 data interface
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad4134_dclk] ; ## FMC_LPC_CLK0_M2C_P
projects/ad4134_fmc: Add FMC pinout descripton * Added txt description of all FMC pins used/unused * Updated constraint files with FMC pinout location Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-09-28 09:47:13 +00:00
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad4134_din[0]] ; ## FMC_LPC_LA00_N_CC
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad4134_din[1]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad4134_din[2]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad4134_din[3]] ; ## FMC_LPC_LA02_N
projects/ad4134_fmc: Add FMC pinout descripton * Added txt description of all FMC pins used/unused * Updated constraint files with FMC pinout location Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-09-28 09:47:13 +00:00
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad4134_odr] ; ## FMC_LPC_LA00_P_CC
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
# ad4134 GPIO lines
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports ad4134_resetn] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad4134_pdn] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad4134_mode] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio0] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio1] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio2] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio3] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio4] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio5] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio6] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio7] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad4134_pinbspi] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports ad4134_dclkio] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports ad4134_dclk_mode] ; ## FMC_LPC_LA14_N