2014-06-12 19:54:25 +00:00
|
|
|
|
|
|
|
|
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
2014-07-03 16:36:37 +00:00
|
|
|
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
|
2014-11-12 19:43:02 +00:00
|
|
|
|
|
|
|
|
p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
|
|
|
|
|
|
|
|
|
|
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3
|
|
|
|
|
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
|
|
|
|
|
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3]
|
|
|
|
|
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk]
|
|
|
|
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \
|
|
|
|
|
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
|
|
|
|
|
|
2014-06-12 19:54:25 +00:00
|
|
|
source ../common/daq2_bd.tcl
|
|
|
|
|
|
