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pluto_hdl_adi/projects/scripts/project-xilinx.mk

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Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
####################################################################################
# Assumes this file is in prpojects/scripts/project-xilinx.mk
HDL_PROJECT_PATH := $(subst scripts/project-xilinx.mk,,$(lastword $(MAKEFILE_LIST)))
HDL_LIBRARY_PATH := $(HDL_PROJECT_PATH)../library/
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
include $(HDL_PROJECT_PATH)../quiet.mk
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
VIVADO := vivado -mode batch -source
CLEAN_TARGET := *.cache
CLEAN_TARGET += *.data
CLEAN_TARGET += *.xpr
CLEAN_TARGET += *.log
CLEAN_TARGET += *.jou
CLEAN_TARGET += xgui
CLEAN_TARGET += *.runs
CLEAN_TARGET += *.srcs
CLEAN_TARGET += *.sdk
CLEAN_TARGET += *.hw
CLEAN_TARGET += *.sim
CLEAN_TARGET += .Xil
CLEAN_TARGET += *.ip_user_files
project-*.mk Update CLEAN targets
2018-03-28 09:44:21 +00:00
CLEAN_TARGET += *.str
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
# Common dependencies that all projects have
M_DEPS += system_project.tcl
M_DEPS += system_bd.tcl
M_DEPS += $(wildcard system_top*.v)
M_DEPS += $(wildcard system_constr.xdc) # Not all projects have this file
M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_project.tcl
M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_env.tcl
M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_board.tcl
Makefile: Change IP component dependency to component definition file Currently the IP component dependency in the Makefile system is the Vivado project file. The project file is only a intermediary product in producing the IP component definition file. If building the component definition file fails or the process is aborted half way through it is possible that the Vivado project file for the IP component exists, but the IP component definition file does not. In this case there will be no attempt to build the IP component definition file when building a project that has a dependency on the IP component. Building the project will fail in this case. To avoid this update the Makefile rules so that the IP component definition file is used as the dependency. In this case the IP component will be re-build if the component definition file does not exist, even if the project file exists. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-26 08:57:03 +00:00
M_DEPS += $(foreach dep,$(LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
.PHONY: all lib clean clean-all
all: lib $(PROJECT_NAME).sdk/system_top.hdf
clean:
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
$(call clean, \
$(CLEAN_TARGET), \
$(HL)$(PROJECT_NAME)$(NC) project)
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
clean-all: clean
@for lib in $(LIB_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} clean; \
done
$(PROJECT_NAME).sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(CLEAN_TARGET)
Add quiet mode to the Makefile system The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-25 07:21:37 +00:00
$(call build, \
$(VIVADO) system_project.tcl, \
$(PROJECT_NAME)_vivado.log, \
$(HL)$(PROJECT_NAME)$(NC) project)
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
lib:
@for lib in $(LIB_DEPS); do \
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} xilinx || exit $$?; \
Add common project Makefile for Xilinx projects The project Makefiles for the Xilinx projects share most of their code. The only difference is the list of project dependencies. Create a file that has the common parts and can be included by the project Makefiles. This drastically reduces the size of the project Makefiles and also allows to change the Makefile implementation without having to re-generate all Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-22 16:15:58 +00:00
done