pluto_hdl_adi/library/axi_dmac/src_fifo_inf.v

// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//  Author: Lars-Peter Clausen <lars@metafoo.de>
// 
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module dmac_src_fifo_inf (
	input clk,
	input resetn,

	input enable,
	output enabled,
	input sync_id,
	output sync_id_ret,

	input [C_ID_WIDTH-1:0] request_id,
	output [C_ID_WIDTH-1:0] response_id,
	input eot,

	input en,
	input [C_DATA_WIDTH-1:0] din,
	output reg overflow,
	input sync,

	input fifo_ready,
	output fifo_valid,
	output [C_DATA_WIDTH-1:0] fifo_data,

	input req_valid,
	output req_ready,
	input [3:0] req_last_burst_length,
	input req_sync_transfer_start
);

parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;

reg valid = 1'b0;
wire ready;
reg [C_DATA_WIDTH-1:0] buffer = 'h00;
reg buffer_sync = 1'b0;

reg needs_sync = 1'b0;
wire has_sync = ~needs_sync | buffer_sync;
wire sync_valid = valid & has_sync;

always @(posedge clk)
begin
	if (resetn == 1'b0) begin
		needs_sync <= 1'b0;
	end else begin
		if (ready && valid && buffer_sync) begin
			needs_sync <= 1'b0;
		end else if (req_valid && req_ready) begin
			needs_sync <= req_sync_transfer_start;
		end
	end
end

always @(posedge clk)
begin
	if (resetn == 1'b0) begin
		valid <= 1'b0;
		overflow <= 1'b0;
	end else begin
		if (enable) begin
			if (en) begin
				buffer <= din;
				buffer_sync <= sync;
				valid <= 1'b1;
			end else if (ready) begin
				valid <= 1'b0;
			end
			overflow <= en & valid & ~ready;
		end else begin
			if (ready)
				valid <= 1'b0;
			overflow <= en;
		end
	end
end

assign sync_id_ret = sync_id;

dmac_data_mover # (
	.C_ID_WIDTH(C_ID_WIDTH),
	.C_DATA_WIDTH(C_DATA_WIDTH),
	.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
	.clk(clk),
	.resetn(resetn),

	.enable(enable),
	.enabled(enabled),
	.sync_id(sync_id),

	.request_id(request_id),
	.response_id(response_id),
	.eot(eot),
	
	.req_valid(req_valid),
	.req_ready(req_ready),
	.req_last_burst_length(req_last_burst_length),

	.s_axi_ready(ready),
	.s_axi_valid(sync_valid),
	.s_axi_data(buffer),
	.m_axi_ready(fifo_ready),
	.m_axi_valid(fifo_valid),
	.m_axi_data(fifo_data)
);

endmodule