2016-05-20 15:46:25 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2017-08-22 20:26:57 +00:00
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create_clock -period "8.138 ns" -name ref_clk0 [get_ports {ref_clk0}]
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create_clock -period "8.138 ns" -name ref_clk1 [get_ports {ref_clk1}]
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2016-05-20 15:46:25 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2017-05-02 11:30:19 +00:00
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set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
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set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
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2017-03-23 13:44:18 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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