2014-12-08 15:44:15 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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2014-12-09 15:37:22 +00:00
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p_plddr3_fifo [current_bd_instance .] axi_ad9234_fifo 256
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2014-12-08 15:44:15 +00:00
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2014-12-15 17:59:25 +00:00
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create_bd_port -dir I -type rst sys_rst
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set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
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2014-12-09 15:37:22 +00:00
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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2014-12-15 17:59:25 +00:00
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connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9234_fifo/sys_rst]
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2014-12-09 15:37:22 +00:00
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connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9234_fifo/DDR3]
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connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9234_fifo/sys_clk]
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create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_fifo/axi_fifo2s/axi] \
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[get_bd_addr_segs axi_ad9234_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
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2014-12-08 15:44:15 +00:00
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2014-12-09 15:37:22 +00:00
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source ../common/fmcadc4_bd.tcl
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2014-12-08 15:44:15 +00:00
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