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pluto_hdl_adi/library/axi_tdd/Makefile

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axi_tdd: Add standalone axi_tdd IP core This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>
2021-06-11 13:45:58 +00:00
####################################################################################
library & projects: Update Makefiles Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-18 13:15:22 +00:00
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
### SPDX short identifier: BSD-1-Clause
axi_tdd: Add standalone axi_tdd IP core This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>
2021-06-11 13:45:58 +00:00
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_tdd
Makefile: Fix misc makefiles from projects and library
2021-09-30 13:20:02 +00:00
GENERIC_DEPS += ../common/up_axi.v
library/axi_tdd: Add generic TDD engine Replaced the existing axi_tdd with the new version * Added DEFAULT_POLARITY synth parameter and RO register * Added TDD_STATUS register * Added TDD_SYNC_RST feature * Used the asy_ prefix for signals which are not synced * Added logic to force the state from ARMED to RUNNING when startup_delay=0 * Added feature to finish the burst when the module is disabled before its completion Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2022-04-07 07:50:43 +00:00
GENERIC_DEPS += ../util_cdc/sync_bits.v
GENERIC_DEPS += ../util_cdc/sync_data.v
GENERIC_DEPS += ../util_cdc/sync_event.v
GENERIC_DEPS += axi_tdd.sv
GENERIC_DEPS += axi_tdd_channel.sv
GENERIC_DEPS += axi_tdd_counter.sv
GENERIC_DEPS += axi_tdd_pkg.sv
GENERIC_DEPS += axi_tdd_regmap.sv
GENERIC_DEPS += axi_tdd_sync_gen.sv
axi_tdd: Add standalone axi_tdd IP core This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>
2021-06-11 13:45:58 +00:00
library: axi_tdd: Make synchronization stage optional Signed-off-by: David Winter <david.winter@analog.com>
2022-03-09 16:44:03 +00:00
XILINX_DEPS += axi_tdd_constr.ttcl
axi_tdd: Add standalone axi_tdd IP core This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>
2021-06-11 13:45:58 +00:00
XILINX_DEPS += axi_tdd_ip.tcl
library/axi_tdd: Add generic TDD engine Replaced the existing axi_tdd with the new version * Added DEFAULT_POLARITY synth parameter and RO register * Added TDD_STATUS register * Added TDD_SYNC_RST feature * Used the asy_ prefix for signals which are not synced * Added logic to force the state from ARMED to RUNNING when startup_delay=0 * Added feature to finish the burst when the module is disabled before its completion Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2022-04-07 07:50:43 +00:00
INTEL_DEPS += axi_tdd_constr.sdc
INTEL_DEPS += axi_tdd_hw.tcl
axi_tdd: Add standalone axi_tdd IP core This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>
2021-06-11 13:45:58 +00:00
include ../scripts/library.mk