64 lines
3.2 KiB
Plaintext
64 lines
3.2 KiB
Plaintext
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# Primary clock definitions
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# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block
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# Maximum values for Link clock:
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# 204B - 15.5 Gbps /40 = 387.5MHz
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# 204C - 24.75 Gbps /66 = 375MHz
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set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
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set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
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set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]]
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set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
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set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
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set rx_link_clk_period [expr 1000/$rx_link_clk]
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set tx_link_clk_period [expr 1000/$tx_link_clk]
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set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]]
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set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]]
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set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]]
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set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]]
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set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width]
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set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width]
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set rx_device_clk_period [expr 1000/$rx_device_clk]
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set tx_device_clk_period [expr 1000/$tx_device_clk]
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# Set reference clock to same frequency as the link clock,
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# this will ease the XCVR out clocks propagation calculation.
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# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE
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create_clock -name refclk -period $rx_link_clk_period [get_ports fpga_refclk_in_p]
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# device clock
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create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clkin8_p]
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create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clkin6_p]
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# Constraint SYSREFs
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# Assumption is that REFCLK and SYSREF have similar propagation delay,
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# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
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set_input_delay -clock [get_clocks rx_device_clk] \
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[get_property PERIOD [get_clocks rx_device_clk]] \
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[get_ports {sysref2_*}]
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set_input_delay -clock [get_clocks tx_device_clk] -add_delay\
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[get_property PERIOD [get_clocks tx_device_clk]] \
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[get_ports {sysref2_*}]
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set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous
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# For transceiver output clocks use reference clock divided by one
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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