2014-04-01 15:46:37 +00:00
|
|
|
|
2015-06-24 09:30:03 +00:00
|
|
|
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
|
|
|
|
|
create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}]
|
|
|
|
|
create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}]
|
2014-04-01 15:46:37 +00:00
|
|
|
|
|
|
|
|
derive_pll_clocks
|
|
|
|
|
derive_clock_uncertainty
|
|
|
|
|
|
2015-06-25 08:25:39 +00:00
|
|
|
set_clock_groups -exclusive \
|
2015-07-23 19:23:10 +00:00
|
|
|
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
|
|
|
|
|
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
|
|
|
|
|
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
|
2014-04-01 15:46:37 +00:00
|
|
|
|
2015-07-01 17:42:08 +00:00
|
|
|
|
