pluto_hdl_adi/projects/pzsdr2/ccbrk_cmos/system_bd.tcl


source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl

ad_ip_parameter clkdiv CONFIG.SEL_0_DIV 2
ad_ip_parameter clkdiv CONFIG.SEL_1_DIV 1

cfg_ad9361_interface CMOS

ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29
ccbrk_cmos: ccbrk copy 2016-03-11 16:19:30 +00:00
pzsdr2- updates 2016-11-15 19:15:55 +00:00			`source ../common/pzsdr2_bd.tcl`
ccbrk_cmos: ccbrk copy 2016-03-11 16:19:30 +00:00			`source ../common/ccbrk_bd.tcl`

pzsdr*: Automatic IP version update 2017-05-02 08:43:32 +00:00			`ad_ip_parameter clkdiv CONFIG.SEL_0_DIV 2`
			`ad_ip_parameter clkdiv CONFIG.SEL_1_DIV 1`
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4 2017-01-18 10:00:10 +00:00
pzsdr2- update ccfmc 2016-11-16 21:27:05 +00:00			`cfg_ad9361_interface CMOS`
ccbrk_cmos: cmos mode 2016-03-11 16:24:35 +00:00
pzsdr*: Automatic IP version update 2017-05-02 08:43:32 +00:00			`ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29`
ad9361- delay initialization 2017-03-15 16:06:49 +00:00