2018-03-22 16:15:58 +00:00
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####################################################################################
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2021-09-13 20:50:01 +00:00
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## Copyright (c) 2018 -2021 Analog Devices, Inc.
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## SPDX short identifier: BSD-1-Clause
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2018-03-22 16:15:58 +00:00
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####################################################################################
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# Assumes this file is in prpojects/scripts/project-xilinx.mk
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HDL_PROJECT_PATH := $(subst scripts/project-xilinx.mk,,$(lastword $(MAKEFILE_LIST)))
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HDL_LIBRARY_PATH := $(HDL_PROJECT_PATH)../library/
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2018-03-25 07:21:37 +00:00
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include $(HDL_PROJECT_PATH)../quiet.mk
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2018-03-22 16:15:58 +00:00
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VIVADO := vivado -mode batch -source
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CLEAN_TARGET := *.cache
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CLEAN_TARGET += *.data
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CLEAN_TARGET += *.xpr
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CLEAN_TARGET += *.log
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CLEAN_TARGET += *.jou
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CLEAN_TARGET += xgui
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CLEAN_TARGET += *.runs
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CLEAN_TARGET += *.srcs
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CLEAN_TARGET += *.sdk
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CLEAN_TARGET += *.hw
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CLEAN_TARGET += *.sim
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CLEAN_TARGET += .Xil
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CLEAN_TARGET += *.ip_user_files
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2018-03-28 09:44:21 +00:00
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CLEAN_TARGET += *.str
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2019-09-25 07:49:51 +00:00
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CLEAN_TARGET += mem_init_sys.txt
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2019-10-04 11:40:12 +00:00
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CLEAN_TARGET += *.csv
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2020-12-16 15:41:19 +00:00
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CLEAN_TARGET += *.hbs
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2021-09-13 13:03:33 +00:00
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CLEAN_TARGET += *.gen
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2021-08-31 12:29:41 +00:00
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CLEAN_TARGET += *.xpe
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CLEAN_TARGET += *.xsa
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2018-03-22 16:15:58 +00:00
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# Common dependencies that all projects have
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M_DEPS += system_project.tcl
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M_DEPS += system_bd.tcl
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M_DEPS += $(wildcard system_top*.v)
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M_DEPS += $(wildcard system_constr.xdc) # Not all projects have this file
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2018-08-14 08:43:32 +00:00
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M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_project_xilinx.tcl
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2018-03-22 16:15:58 +00:00
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M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_env.tcl
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M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_board.tcl
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2018-03-26 08:57:03 +00:00
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M_DEPS += $(foreach dep,$(LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
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2018-03-22 16:15:58 +00:00
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2019-09-11 08:01:30 +00:00
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.PHONY: all lib clean clean-all
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2021-08-31 12:29:41 +00:00
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all: lib $(PROJECT_NAME).sdk/system_top.xsa
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2018-03-22 16:15:58 +00:00
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clean:
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2019-04-17 10:33:17 +00:00
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-rm -f reference.dcp
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2018-03-25 07:21:37 +00:00
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$(call clean, \
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$(CLEAN_TARGET), \
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$(HL)$(PROJECT_NAME)$(NC) project)
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2018-03-22 16:15:58 +00:00
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clean-all: clean
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@for lib in $(LIB_DEPS); do \
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$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} clean; \
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done
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2019-04-17 10:33:17 +00:00
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MODE ?= "default"
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2021-08-31 12:29:41 +00:00
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$(PROJECT_NAME).sdk/system_top.xsa: $(M_DEPS)
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2019-04-17 10:33:17 +00:00
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@if [ $(MODE) = incr ]; then \
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if [ -f */impl_1/system_top_routed.dcp ]; then \
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echo Found previous run result at `ls */impl_1/system_top_routed.dcp`; \
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cp -u */impl_1/system_top_routed.dcp ./reference.dcp ; \
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fi; \
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if [ -f ./reference.dcp ]; then \
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echo Using reference checkpoint for incremental compilation; \
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fi; \
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2019-04-22 15:15:44 +00:00
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else \
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rm -f reference.dcp; \
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fi;
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2018-03-22 16:15:58 +00:00
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-rm -rf $(CLEAN_TARGET)
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2018-03-25 07:21:37 +00:00
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$(call build, \
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$(VIVADO) system_project.tcl, \
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$(PROJECT_NAME)_vivado.log, \
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$(HL)$(PROJECT_NAME)$(NC) project)
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2018-03-22 16:15:58 +00:00
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lib:
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@for lib in $(LIB_DEPS); do \
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2018-03-27 09:21:09 +00:00
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$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} xilinx || exit $$?; \
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2018-03-22 16:15:58 +00:00
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done
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