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pluto_hdl_adi/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl

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adxcvr- initial commit
2016-07-08 17:56:08 +00:00
## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
xcvr- altera/xilinx split
2016-08-04 17:26:10 +00:00
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
adi_ip_create axi_adxcvr
adi_ip_files axi_adxcvr [list \
"$ad_hdl_dir/library/common/up_axi.v" \
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"axi_adxcvr_es.v" \
"axi_adxcvr_up.v" \
"axi_adxcvr_mdrp.v" \
"axi_adxcvr_mstatus.v" \
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
"axi_adxcvr.v" ]
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
axi_adxcvr: Update the packaging script to fix infer mm issues - Change the clock and reset port name of the AXI slave interface to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties process to infer the interface. - Define an address space reference to the m_axi interface.
2017-01-19 13:16:04 +00:00
adi_ip_properties axi_adxcvr
adi_ip_infer_mm_interfaces axi_adxcvr
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
adi_init_bd_tcl
library/IPs: Auto-generate bd.tcl Update Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to auto-generate bd.tcl for: - axi_ad5766/axi_ad5766_ip.tcl - axi_ad6676/axi_ad6676_ip.tcl - axi_ad9122/axi_ad9122_ip.tcl - axi_ad9144/axi_ad9144_ip.tcl - axi_ad9152/axi_ad9152_ip.tcl - axi_ad9162/axi_ad9162_ip.tcl - axi_ad9250/axi_ad9250_ip.tcl - axi_ad9265/axi_ad9265_ip.tcl - axi_ad9361/axi_ad9361_ip.tcl - axi_ad9371/axi_ad9371_ip.tcl - axi_ad9434/axi_ad9434_ip.tcl - axi_ad9467/axi_ad9467_ip.tcl - axi_ad9625/axi_ad9625_ip.tcl - axi_ad9671/axi_ad9671_ip.tcl - axi_ad9680/axi_ad9680_ip.tcl - axi_ad9684/axi_ad9684_ip.tcl - axi_ad9739a/axi_ad9739a_ip.tcl - axi_ad9963/axi_ad9963_ip.tcl - axi_adrv9009/axi_adrv9009_ip.tcl - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl - axi_hdmi_tx/axi_hdmi_tx_ip.tcl - xilinx/axi_adxcvr/Makefile - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl - xilinx/util_adxcvr/Makefile - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-14 15:25:36 +00:00
adi_ip_bd axi_adxcvr "bd/bd.tcl"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
axi_adxcvr: Update the packaging script to fix infer mm issues - Change the clock and reset port name of the AXI slave interface to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties process to infer the interface. - Define an address space reference to the m_axi interface.
2017-01-19 13:16:04 +00:00
set_property master_address_space_ref m_axi \
[ipx::get_bus_interfaces m_axi \
-of_objects [ipx::current_core]]
adxcvr- added a space?
2016-07-29 13:38:08 +00:00
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
for {set n 0} {$n < 16} {incr n} {
if {($n%4) == 0} {
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
"wdata up_cm_wdata_${n} "\
"rdata up_cm_rdata_${n} "\
"ready up_cm_ready_${n} "]
}
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
axi/util_adxcvr: Add register to control eyescan reset
2018-11-08 13:54:15 +00:00
"reset up_es_reset_${n} "\
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\
"ready up_es_ready_${n} "]
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"pll_locked up_ch_pll_locked_${n} "\
"rst up_ch_rst_${n} "\
"user_ready up_ch_user_ready_${n} "\
"rst_done up_ch_rst_done_${n} "\
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
"prbsforceerr up_ch_prbsforceerr_${n}"\
"prbssel up_ch_prbssel_${n} "\
"prbscntreset up_ch_prbscntreset_${n}"\
"prbserr up_ch_prbserr_${n} "\
"prbslocked up_ch_prbslocked_${n} "\
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
"rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\
"out_clk_sel up_ch_out_clk_sel_${n} "\
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
"tx_diffctrl up_ch_tx_diffctrl_${n} "\
"tx_postcursor up_ch_tx_postcursor_${n} "\
"tx_precursor up_ch_tx_precursor_${n} "\
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
"enb up_ch_enb_${n} "\
"addr up_ch_addr_${n} "\
"wr up_ch_wr_${n} "\
"wdata up_ch_wdata_${n} "\
"rdata up_ch_rdata_${n} "\
"ready up_ch_ready_${n} "]
}
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
axi_adxcvr- add m_axi associated clock
2017-02-02 16:15:59 +00:00
set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
axi_adxcvr- status output for jesd ip
2016-07-15 14:15:56 +00:00
set_property enablement_dependency \
{spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \
[ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]]
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
adxcvr- initial commit
2016-07-08 17:56:08 +00:00
ipx::save_core [ipx::current_core]