pluto_hdl_adi/library/axi_dac_interpolate/axi_dac_interpolate.v

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dac_interpolate(
input dac_clk,
input dac_rst,
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input [15:0] dac_data_a,
input [15:0] dac_data_b,
input dac_valid_a,
input dac_valid_b,
output [15:0] dac_int_data_a,
output [15:0] dac_int_data_b,
output dac_int_valid_a,
output dac_int_valid_b,
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// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal signals
wire up_clk;
wire up_rstn;
wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [ 4:0] up_raddr;
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wire [31:0] interpolation_ratio_a;
wire [31:0] interpolation_ratio_b;
wire [ 2:0] filter_mask_a;
wire [ 2:0] filter_mask_b;
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wire dma_transfer_suspend;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
axi_dac_interpolate_filter i_filter_a (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
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.dac_data (dac_data_a),
.dac_valid (dac_valid_a),
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.dac_int_data (dac_int_data_a),
.dac_int_valid (dac_int_valid_a),
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.filter_mask (filter_mask_a),
.interpolation_ratio (interpolation_ratio_a),
.dma_transfer_suspend (dma_transfer_suspend)
);
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axi_dac_interpolate_filter i_filter_b (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
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.dac_data (dac_data_b),
.dac_valid (dac_valid_b),
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.dac_int_data (dac_int_data_b),
.dac_int_valid (dac_int_valid_b),
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.filter_mask (filter_mask_b),
.interpolation_ratio (interpolation_ratio_b),
.dma_transfer_suspend (dma_transfer_suspend)
);
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axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
.clk (dac_clk),
.dac_interpolation_ratio_a (interpolation_ratio_a),
.dac_filter_mask_a (filter_mask_a),
.dac_interpolation_ratio_b (interpolation_ratio_b),
.dac_filter_mask_b (filter_mask_b),
.dma_transfer_suspend (dma_transfer_suspend),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH(7),
.ADDRESS_WIDTH(5)
) i_up_axi (
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.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************