2014-10-07 16:41:54 +00:00
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2014-10-29 17:29:42 +00:00
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create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
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create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}]
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2014-10-07 16:41:54 +00:00
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create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
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create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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2014-10-29 17:29:42 +00:00
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set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ]
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set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
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set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
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set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
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set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
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set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
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2014-10-07 16:41:54 +00:00
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2014-10-29 17:29:42 +00:00
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set_false_path -from {sys_resetn} -to *
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set_false_path -from * -to {sys_resetn}
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