zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl

132 lines
5.8 KiB
Tcl
Raw Normal View History

Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
## ADC FIFO depth in samples per converter
ad9081_fmca_ebz: Np 12 support 204B functional 204C functional
2020-11-06 14:49:05 +00:00
set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024]
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
## DAC FIFO depth in samples per converter
ad9081_fmca_ebz: Np 12 support 204B functional 204C functional
2020-11-06 14:49:05 +00:00
set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024]
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad9081_fmca_ebz: Update path to common block design Use absolute paths so ad9082 wrapper project can include the system_bd.tcl instead of duplicating code.
2021-05-05 11:42:54 +00:00
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
ad9081: Parameters and header update Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2023-05-08 12:01:09 +00:00
if {$INTF_CFG != "TX"} {
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
}
if {$INTF_CFG != "RX"} {
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
}
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
# Parameters for 15.5Gpbs lane rate
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x2b
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x4040
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3002
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2 0x1E9
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x1
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_XMODE_SEL 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs Organize XCVR params based on lane rate
2021-04-19 13:57:19 +00:00
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x54
ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2019-12-05 09:20:08 +00:00
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs Organize XCVR params based on lane rate
2021-04-19 13:57:19 +00:00
# 204C params 16.5Gbps..24.75Gpbs
if {$ad_project_params(JESD_MODE) == "64B66B"} {
ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing This commit fixes the 16.5Gbps lane rate case where the link drops after few seconds an initial successful link up happens. A few seconds delayed calibration process can workaround this but with having the differential drivers swing increased this is no longer required.
2021-05-10 14:58:23 +00:00
# Set higher swing for the diff driver, other case 16.5Gbps won't work
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_DIFFCTRL 0xC
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs Organize XCVR params based on lane rate
2021-04-19 13:57:19 +00:00
# Lane rate indepentent parameters
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6060
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 2
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 2
ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG2 0x281C
ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG3 0x4120
ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing This commit fixes the 16.5Gbps lane rate case where the link drops after few seconds an initial successful link up happens. A few seconds delayed calibration process can workaround this but with having the differential drivers swing increased this is no longer required.
2021-05-10 14:58:23 +00:00
# Lane rate indepentent QPLL parameters
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0x600
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x331c
# Lane rate dependent QPLL params (these match for 16.5 Gbps and 24.75 Gpbs)
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF1_CFG 0x400
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x33f
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2 0x0FC1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2_G3 0x0FC1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x03
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs Organize XCVR params based on lane rate
2021-04-19 13:57:19 +00:00
# set dividers for 24.75Gbps, are overwritten by software
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 66
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 2
if {$ad_project_params(RX_LANE_RATE) < 20} {
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x0104
} else {
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x6
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3004
}
if {$ad_project_params(TX_LANE_RATE) < 20} {
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C2
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x0100
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x1000
ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 0
} else {
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 3
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C6
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xF800
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3000
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 1
}
}