2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2019-01-22 13:19:09 +00:00
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set dac_fifo_name avl_ad9371_tx_fifo
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set dac_data_width 128
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set dac_dma_data_width 128
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2016-08-16 12:34:10 +00:00
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2021-01-05 09:15:00 +00:00
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# NOTE: The real lane rate is 4915.2 Gbps (Tx/RX/Rx_Obs), with a real reference
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# clock frequency of 122.88 MHz. A round up needed because the fPLL's
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# configuration interface does not support fractional numbers.
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2017-08-22 20:26:57 +00:00
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# ad9371_tx JESD204
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add_instance ad9371_tx_jesd204 adi_jesd204
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set_instance_parameter_value ad9371_tx_jesd204 {ID} {0}
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set_instance_parameter_value ad9371_tx_jesd204 {TX_OR_RX_N} {1}
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2021-01-05 09:15:00 +00:00
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set_instance_parameter_value ad9371_tx_jesd204 {LANE_RATE} {4920}
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set_instance_parameter_value ad9371_tx_jesd204 {REFCLK_FREQUENCY} {123}
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2017-08-22 20:26:57 +00:00
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set_instance_parameter_value ad9371_tx_jesd204 {NUM_OF_LANES} {4}
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set_instance_parameter_value ad9371_tx_jesd204 {LANE_MAP} {3 0 1 2}
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set_instance_parameter_value ad9371_tx_jesd204 {SOFT_PCS} {false}
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add_connection sys_clk.clk ad9371_tx_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9371_tx_jesd204.sys_resetn
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2016-10-26 17:13:49 +00:00
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add_interface tx_ref_clk clock sink
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2017-08-22 20:26:57 +00:00
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set_interface_property tx_ref_clk EXPORT_OF ad9371_tx_jesd204.ref_clk
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add_interface tx_serial_data conduit end
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set_interface_property tx_serial_data EXPORT_OF ad9371_tx_jesd204.serial_data
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2016-08-16 12:34:10 +00:00
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add_interface tx_sysref conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property tx_sysref EXPORT_OF ad9371_tx_jesd204.sysref
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2016-10-26 17:13:49 +00:00
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add_interface tx_sync conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property tx_sync EXPORT_OF ad9371_tx_jesd204.sync
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# ad9371_rx JESD204
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add_instance ad9371_rx_jesd204 adi_jesd204
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set_instance_parameter_value ad9371_rx_jesd204 {ID} {1}
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set_instance_parameter_value ad9371_rx_jesd204 {TX_OR_RX_N} {0}
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2021-01-05 09:15:00 +00:00
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set_instance_parameter_value ad9371_rx_jesd204 {LANE_RATE} {4920}
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set_instance_parameter_value ad9371_rx_jesd204 {REFCLK_FREQUENCY} {123}
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2017-08-22 20:26:57 +00:00
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set_instance_parameter_value ad9371_rx_jesd204 {NUM_OF_LANES} {2}
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set_instance_parameter_value ad9371_rx_jesd204 {SOFT_PCS} {false}
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add_connection sys_clk.clk ad9371_rx_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9371_rx_jesd204.sys_resetn
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2016-10-26 17:13:49 +00:00
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add_interface rx_ref_clk clock sink
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_ref_clk EXPORT_OF ad9371_rx_jesd204.ref_clk
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add_interface rx_serial_data conduit end
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set_interface_property rx_serial_data EXPORT_OF ad9371_rx_jesd204.serial_data
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2016-10-26 17:13:49 +00:00
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add_interface rx_sysref conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_sysref EXPORT_OF ad9371_rx_jesd204.sysref
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2016-10-26 17:13:49 +00:00
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add_interface rx_sync conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_sync EXPORT_OF ad9371_rx_jesd204.sync
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# ad9371_rx_os JESD204
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add_instance ad9371_rx_os_jesd204 adi_jesd204
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set_instance_parameter_value ad9371_rx_os_jesd204 {ID} {1}
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set_instance_parameter_value ad9371_rx_os_jesd204 {TX_OR_RX_N} {0}
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2021-01-05 09:15:00 +00:00
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set_instance_parameter_value ad9371_rx_os_jesd204 {LANE_RATE} {4920}
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set_instance_parameter_value ad9371_rx_os_jesd204 {REFCLK_FREQUENCY} {123}
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2017-08-22 20:26:57 +00:00
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set_instance_parameter_value ad9371_rx_os_jesd204 {SOFT_PCS} {false}
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set_instance_parameter_value ad9371_rx_os_jesd204 {NUM_OF_LANES} {2}
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add_connection sys_clk.clk ad9371_rx_os_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9371_rx_os_jesd204.sys_resetn
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2016-10-26 17:13:49 +00:00
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add_interface rx_os_ref_clk clock sink
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_os_ref_clk EXPORT_OF ad9371_rx_os_jesd204.ref_clk
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add_interface rx_os_serial_data conduit end
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set_interface_property rx_os_serial_data EXPORT_OF ad9371_rx_os_jesd204.serial_data
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2016-10-26 17:13:49 +00:00
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add_interface rx_os_sysref conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_os_sysref EXPORT_OF ad9371_rx_os_jesd204.sysref
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2016-10-26 17:13:49 +00:00
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add_interface rx_os_sync conduit end
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2017-08-22 20:26:57 +00:00
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set_interface_property rx_os_sync EXPORT_OF ad9371_rx_os_jesd204.sync
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2016-08-16 12:34:10 +00:00
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2020-05-22 07:24:13 +00:00
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# ad9371 TPL cores
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add_instance axi_ad9371_tx ad_ip_jesd204_tpl_dac
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set_instance_parameter_value axi_ad9371_tx {ID} {0}
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set_instance_parameter_value axi_ad9371_tx {NUM_CHANNELS} {4}
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set_instance_parameter_value axi_ad9371_tx {NUM_LANES} {4}
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set_instance_parameter_value axi_ad9371_tx {BITS_PER_SAMPLE} {16}
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set_instance_parameter_value axi_ad9371_tx {CONVERTER_RESOLUTION} {16}
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add_instance axi_ad9371_rx ad_ip_jesd204_tpl_adc
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set_instance_parameter_value axi_ad9371_rx {ID} {0}
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set_instance_parameter_value axi_ad9371_rx {NUM_CHANNELS} {4}
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set_instance_parameter_value axi_ad9371_rx {NUM_LANES} {2}
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set_instance_parameter_value axi_ad9371_rx {BITS_PER_SAMPLE} {16}
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set_instance_parameter_value axi_ad9371_rx {CONVERTER_RESOLUTION} {16}
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set_instance_parameter_value axi_ad9371_rx {TWOS_COMPLEMENT} {1}
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add_instance axi_ad9371_rx_os ad_ip_jesd204_tpl_adc
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set_instance_parameter_value axi_ad9371_rx_os {ID} {1}
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set_instance_parameter_value axi_ad9371_rx_os {NUM_CHANNELS} {2}
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set_instance_parameter_value axi_ad9371_rx_os {NUM_LANES} {2}
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set_instance_parameter_value axi_ad9371_rx_os {BITS_PER_SAMPLE} {16}
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set_instance_parameter_value axi_ad9371_rx_os {CONVERTER_RESOLUTION} {16}
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set_instance_parameter_value axi_ad9371_rx_os {TWOS_COMPLEMENT} {1}
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add_connection sys_clk.clk axi_ad9371_tx.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_tx.s_axi_reset
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add_connection ad9371_tx_jesd204.link_clk axi_ad9371_tx.link_clk
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add_connection axi_ad9371_tx.link_data ad9371_tx_jesd204.link_data
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add_connection sys_clk.clk axi_ad9371_rx.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_rx.s_axi_reset
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add_connection ad9371_rx_jesd204.link_clk axi_ad9371_rx.link_clk
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add_connection ad9371_rx_jesd204.link_sof axi_ad9371_rx.if_link_sof
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add_connection ad9371_rx_jesd204.link_data axi_ad9371_rx.link_data
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add_connection sys_clk.clk axi_ad9371_rx_os.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_rx_os.s_axi_reset
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add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371_rx_os.link_clk
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add_connection ad9371_rx_os_jesd204.link_sof axi_ad9371_rx_os.if_link_sof
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add_connection ad9371_rx_os_jesd204.link_data axi_ad9371_rx_os.link_data
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2016-10-26 17:13:49 +00:00
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# pack(s) & unpack(s)
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2018-10-04 10:35:14 +00:00
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add_instance axi_ad9371_tx_upack util_upack2
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_tx_upack {NUM_OF_CHANNELS} {4}
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2018-10-04 10:35:14 +00:00
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set_instance_parameter_value axi_ad9371_tx_upack {SAMPLES_PER_CHANNEL} {2}
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set_instance_parameter_value axi_ad9371_tx_upack {SAMPLE_DATA_WIDTH} {16}
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set_instance_parameter_value axi_ad9371_tx_upack {INTERFACE_TYPE} {1}
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add_connection ad9371_tx_jesd204.link_clk axi_ad9371_tx_upack.clk
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add_connection ad9371_tx_jesd204.link_reset axi_ad9371_tx_upack.reset
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2020-05-22 07:24:13 +00:00
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add_connection axi_ad9371_tx_upack.dac_ch_0 axi_ad9371_tx.dac_ch_0
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add_connection axi_ad9371_tx_upack.dac_ch_1 axi_ad9371_tx.dac_ch_1
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add_connection axi_ad9371_tx_upack.dac_ch_2 axi_ad9371_tx.dac_ch_2
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add_connection axi_ad9371_tx_upack.dac_ch_3 axi_ad9371_tx.dac_ch_3
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2016-10-26 17:13:49 +00:00
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2018-10-04 10:35:14 +00:00
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add_instance axi_ad9371_rx_cpack util_cpack2
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_cpack {NUM_OF_CHANNELS} {4}
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2018-10-04 10:35:14 +00:00
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set_instance_parameter_value axi_ad9371_rx_cpack {SAMPLES_PER_CHANNEL} {1}
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set_instance_parameter_value axi_ad9371_rx_cpack {SAMPLE_DATA_WIDTH} {16}
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add_connection ad9371_rx_jesd204.link_clk axi_ad9371_rx_cpack.clk
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add_connection ad9371_rx_jesd204.link_reset axi_ad9371_rx_cpack.reset
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2020-05-22 07:24:13 +00:00
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add_connection axi_ad9371_rx.adc_ch_0 axi_ad9371_rx_cpack.adc_ch_0
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add_connection axi_ad9371_rx.adc_ch_1 axi_ad9371_rx_cpack.adc_ch_1
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add_connection axi_ad9371_rx.adc_ch_2 axi_ad9371_rx_cpack.adc_ch_2
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add_connection axi_ad9371_rx.adc_ch_3 axi_ad9371_rx_cpack.adc_ch_3
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add_connection axi_ad9371_rx_cpack.if_fifo_wr_overflow axi_ad9371_rx.if_adc_dovf
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2016-10-26 17:13:49 +00:00
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2018-10-04 10:35:14 +00:00
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add_instance axi_ad9371_rx_os_cpack util_cpack2
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_os_cpack {NUM_OF_CHANNELS} {2}
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2018-10-04 10:35:14 +00:00
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set_instance_parameter_value axi_ad9371_rx_os_cpack {SAMPLES_PER_CHANNEL} {2}
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set_instance_parameter_value axi_ad9371_rx_os_cpack {SAMPLE_DATA_WIDTH} {16}
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add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371_rx_os_cpack.clk
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add_connection ad9371_rx_os_jesd204.link_reset axi_ad9371_rx_os_cpack.reset
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2020-05-22 07:24:13 +00:00
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add_connection axi_ad9371_rx_os.adc_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0
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add_connection axi_ad9371_rx_os.adc_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1
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add_connection axi_ad9371_rx_os_cpack.if_fifo_wr_overflow axi_ad9371_rx_os.if_adc_dovf
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2016-10-26 17:13:49 +00:00
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2017-06-20 10:58:59 +00:00
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# dac fifo
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2017-05-18 16:54:04 +00:00
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2019-01-22 13:19:09 +00:00
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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2017-03-06 15:33:52 +00:00
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add_interface tx_fifo_bypass conduit end
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2017-04-21 10:27:35 +00:00
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set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9371_tx_fifo.if_bypass
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2016-10-26 17:13:49 +00:00
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2017-08-22 20:26:57 +00:00
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add_connection ad9371_tx_jesd204.link_clk avl_ad9371_tx_fifo.if_dac_clk
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add_connection ad9371_tx_jesd204.link_reset avl_ad9371_tx_fifo.if_dac_rst
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2018-10-04 10:35:14 +00:00
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add_connection axi_ad9371_tx_upack.if_packed_fifo_rd_en avl_ad9371_tx_fifo.if_dac_valid
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add_connection avl_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_packed_fifo_rd_data
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2020-05-22 07:24:13 +00:00
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add_connection avl_ad9371_tx_fifo.if_dac_dunf axi_ad9371_tx.if_dac_dunf
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2017-03-01 20:34:04 +00:00
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2016-10-26 17:13:49 +00:00
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# dac & adc dma
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9371_tx_dma axi_dmac
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_tx_dma {ID} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1}
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2017-03-01 20:34:04 +00:00
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {1}
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16}
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2019-05-16 07:13:49 +00:00
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set_instance_parameter_value axi_ad9371_tx_dma {HAS_AXIS_TLAST} {1}
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2017-04-21 10:27:35 +00:00
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add_connection sys_dma_clk.clk avl_ad9371_tx_fifo.if_dma_clk
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add_connection sys_dma_clk.clk_reset avl_ad9371_tx_fifo.if_dma_rst
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2017-03-01 20:34:04 +00:00
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add_connection sys_dma_clk.clk axi_ad9371_tx_dma.if_m_axis_aclk
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2019-05-16 07:13:49 +00:00
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add_connection axi_ad9371_tx_dma.m_axis avl_ad9371_tx_fifo.s_axis
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2017-04-21 10:27:35 +00:00
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add_connection axi_ad9371_tx_dma.if_m_axis_xfer_req avl_ad9371_tx_fifo.if_dma_xfer_req
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2016-10-26 17:13:49 +00:00
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add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9371_tx_dma.m_src_axi_reset
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9371_rx_dma axi_dmac
|
2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_dma {ID} {0}
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_SRC} {0}
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2017-10-04 10:29:09 +00:00
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set_instance_parameter_value axi_ad9371_rx_dma {SYNC_TRANSFER_START} {1}
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0}
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0}
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2017-06-20 10:58:59 +00:00
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set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {2}
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2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16}
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2017-08-22 20:26:57 +00:00
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add_connection ad9371_rx_jesd204.link_clk axi_ad9371_rx_dma.if_fifo_wr_clk
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2018-10-04 10:35:14 +00:00
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add_connection axi_ad9371_rx_cpack.if_packed_fifo_wr_en axi_ad9371_rx_dma.if_fifo_wr_en
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add_connection axi_ad9371_rx_cpack.if_packed_fifo_wr_sync axi_ad9371_rx_dma.if_fifo_wr_sync
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add_connection axi_ad9371_rx_cpack.if_packed_fifo_wr_data axi_ad9371_rx_dma.if_fifo_wr_din
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add_connection axi_ad9371_rx_dma.if_fifo_wr_overflow axi_ad9371_rx_cpack.if_packed_fifo_wr_overflow
|
2016-10-26 17:13:49 +00:00
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|
add_connection sys_clk.clk axi_ad9371_rx_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9371_rx_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_ad9371_rx_dma.m_dest_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9371_rx_dma.m_dest_axi_reset
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|
2017-05-12 17:40:14 +00:00
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|
add_instance axi_ad9371_rx_os_dma axi_dmac
|
2016-10-26 17:13:49 +00:00
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set_instance_parameter_value axi_ad9371_rx_os_dma {ID} {0}
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set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_DEST} {128}
|
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set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_SRC} {0}
|
2017-10-04 10:29:09 +00:00
|
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|
set_instance_parameter_value axi_ad9371_rx_os_dma {SYNC_TRANSFER_START} {1}
|
2016-10-26 17:13:49 +00:00
|
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|
set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0}
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set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0}
|
2017-06-20 10:58:59 +00:00
|
|
|
set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {2}
|
2016-10-26 17:13:49 +00:00
|
|
|
set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16}
|
2017-08-22 20:26:57 +00:00
|
|
|
add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371_rx_os_dma.if_fifo_wr_clk
|
2018-10-04 10:35:14 +00:00
|
|
|
add_connection axi_ad9371_rx_os_cpack.if_packed_fifo_wr_en axi_ad9371_rx_os_dma.if_fifo_wr_en
|
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|
|
add_connection axi_ad9371_rx_os_cpack.if_packed_fifo_wr_sync axi_ad9371_rx_os_dma.if_fifo_wr_sync
|
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|
add_connection axi_ad9371_rx_os_cpack.if_packed_fifo_wr_data axi_ad9371_rx_os_dma.if_fifo_wr_din
|
|
|
|
|
add_connection axi_ad9371_rx_os_dma.if_fifo_wr_overflow axi_ad9371_rx_os_cpack.if_packed_fifo_wr_overflow
|
2016-10-26 17:13:49 +00:00
|
|
|
add_connection sys_clk.clk axi_ad9371_rx_os_dma.s_axi_clock
|
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|
|
add_connection sys_clk.clk_reset axi_ad9371_rx_os_dma.s_axi_reset
|
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|
|
add_connection sys_dma_clk.clk axi_ad9371_rx_os_dma.m_dest_axi_clock
|
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|
|
add_connection sys_dma_clk.clk_reset axi_ad9371_rx_os_dma.m_dest_axi_reset
|
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|
# ad9371 gpio
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance avl_ad9371_gpio altera_avalon_pio
|
2016-10-26 17:13:49 +00:00
|
|
|
set_instance_parameter_value avl_ad9371_gpio {direction} {Bidir}
|
|
|
|
|
set_instance_parameter_value avl_ad9371_gpio {generateIRQ} {1}
|
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|
|
set_instance_parameter_value avl_ad9371_gpio {width} {19}
|
|
|
|
|
add_connection sys_clk.clk avl_ad9371_gpio.clk
|
|
|
|
|
add_connection sys_clk.clk_reset avl_ad9371_gpio.reset
|
2017-03-27 17:51:45 +00:00
|
|
|
add_interface ad9371_gpio conduit end
|
|
|
|
|
set_interface_property ad9371_gpio EXPORT_OF avl_ad9371_gpio.external_connection
|
2016-10-26 17:13:49 +00:00
|
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|
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|
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|
|
# reconfig sharing
|
|
|
|
|
|
2017-08-22 20:26:57 +00:00
|
|
|
for {set i 0} {$i < 4} {incr i} {
|
|
|
|
|
add_instance avl_adxcfg_${i} avl_adxcfg
|
2019-04-16 07:28:29 +00:00
|
|
|
set_instance_parameter_value avl_adxcfg_${i} {ADDRESS_WIDTH} $xcvr_reconfig_addr_width
|
2017-08-22 20:26:57 +00:00
|
|
|
add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
|
|
|
|
|
add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
|
|
|
|
|
add_connection avl_adxcfg_${i}.rcfg_m0 ad9371_tx_jesd204.phy_reconfig_${i}
|
|
|
|
|
|
|
|
|
|
if {$i < 2} {
|
|
|
|
|
add_connection avl_adxcfg_${i}.rcfg_m1 ad9371_rx_jesd204.phy_reconfig_${i}
|
|
|
|
|
} else {
|
|
|
|
|
set j [expr $i - 2]
|
|
|
|
|
add_connection avl_adxcfg_${i}.rcfg_m1 ad9371_rx_os_jesd204.phy_reconfig_${j}
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-08-16 12:34:10 +00:00
|
|
|
|
|
|
|
|
# addresses
|
|
|
|
|
|
2017-08-22 20:26:57 +00:00
|
|
|
ad_cpu_interconnect 0x00020000 ad9371_tx_jesd204.link_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00024000 ad9371_tx_jesd204.link_management
|
|
|
|
|
ad_cpu_interconnect 0x00025000 ad9371_tx_jesd204.link_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00026000 ad9371_tx_jesd204.lane_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0002c000 axi_ad9371_tx_dma.s_axi
|
|
|
|
|
|
|
|
|
|
ad_cpu_interconnect 0x00030000 ad9371_rx_jesd204.link_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00034000 ad9371_rx_jesd204.link_management
|
|
|
|
|
ad_cpu_interconnect 0x00035000 ad9371_rx_jesd204.link_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x0003c000 axi_ad9371_rx_dma.s_axi
|
|
|
|
|
|
|
|
|
|
ad_cpu_interconnect 0x00040000 ad9371_rx_os_jesd204.link_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00044000 ad9371_rx_os_jesd204.link_management
|
|
|
|
|
ad_cpu_interconnect 0x00045000 ad9371_rx_os_jesd204.link_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00048000 avl_adxcfg_2.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x00049000 avl_adxcfg_3.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x0004c000 axi_ad9371_rx_os_dma.s_axi
|
|
|
|
|
|
2020-05-22 07:24:13 +00:00
|
|
|
ad_cpu_interconnect 0x00050000 axi_ad9371_rx.s_axi
|
|
|
|
|
ad_cpu_interconnect 0x00054000 axi_ad9371_tx.s_axi
|
|
|
|
|
ad_cpu_interconnect 0x00058000 axi_ad9371_rx_os.s_axi
|
2017-08-22 20:26:57 +00:00
|
|
|
ad_cpu_interconnect 0x00060000 avl_ad9371_gpio.s1
|
2016-10-26 17:13:49 +00:00
|
|
|
|
|
|
|
|
# dma interconnects
|
|
|
|
|
|
|
|
|
|
ad_dma_interconnect axi_ad9371_tx_dma.m_src_axi
|
|
|
|
|
ad_dma_interconnect axi_ad9371_rx_dma.m_dest_axi
|
|
|
|
|
ad_dma_interconnect axi_ad9371_rx_os_dma.m_dest_axi
|
2016-08-16 12:34:10 +00:00
|
|
|
|
|
|
|
|
# interrupts
|
|
|
|
|
|
2016-10-26 17:13:49 +00:00
|
|
|
ad_cpu_interrupt 11 axi_ad9371_tx_dma.interrupt_sender
|
|
|
|
|
ad_cpu_interrupt 12 axi_ad9371_rx_dma.interrupt_sender
|
|
|
|
|
ad_cpu_interrupt 13 axi_ad9371_rx_os_dma.interrupt_sender
|
|
|
|
|
ad_cpu_interrupt 14 avl_ad9371_gpio.irq
|
|
|
|
|
|
