zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/fmcomms6/common/fmcomms6_bd.tcl

89 lines
3.6 KiB
Tcl
Raw Normal View History

Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc interface
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_or_in_p
create_bd_port -dir I adc_or_in_n
create_bd_port -dir I -from 15 -to 0 adc_data_in_p
create_bd_port -dir I -from 15 -to 0 adc_data_in_n
# adc peripherals
set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi_ad9652]
set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
set axi_ad9652_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 axi_ad9652_adc_fifo]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9652_adc_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $axi_ad9652_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $axi_ad9652_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $axi_ad9652_adc_fifo
set data_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
# connections (adc)
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
ad_connect adc_clk_in_p axi_ad9652/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9652/adc_clk_in_n
ad_connect adc_or_in_p axi_ad9652/adc_or_in_p
ad_connect adc_or_in_n axi_ad9652/adc_or_in_n
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_connect adc_data_in_p axi_ad9652/adc_data_in_p
ad_connect adc_data_in_n axi_ad9652/adc_data_in_n
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
ad_connect axi_ad9652/adc_clk axi_ad9652_adc_fifo/din_clk
ad_connect axi_ad9652/adc_rst axi_ad9652_adc_fifo/din_rst
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_connect sys_200m_clk axi_ad9652/delay_clk
ad_connect sys_200m_clk axi_ad9652_dma/fifo_wr_clk
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
fmcomms6: Fixed reset connection for cpack core
2015-12-16 08:36:33 +00:00
ad_connect sys_200m_clk data_pack/adc_clk
ad_connect sys_cpu_reset data_pack/adc_rst
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 08:31:08 +00:00
ad_connect axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0
ad_connect axi_ad9652/adc_valid_0 axi_ad9652_adc_fifo/din_valid_0
ad_connect axi_ad9652/adc_data_0 axi_ad9652_adc_fifo/din_data_0
ad_connect axi_ad9652/adc_enable_1 axi_ad9652_adc_fifo/din_enable_1
ad_connect axi_ad9652/adc_valid_1 axi_ad9652_adc_fifo/din_valid_1
ad_connect axi_ad9652/adc_data_1 axi_ad9652_adc_fifo/din_data_1
ad_connect sys_200m_clk axi_ad9652_adc_fifo/dout_clk
ad_connect sys_cpu_resetn axi_ad9652_adc_fifo/dout_rstn
ad_connect axi_ad9652_adc_fifo/dout_valid_0 data_pack/adc_valid_0
ad_connect axi_ad9652_adc_fifo/dout_enable_0 data_pack/adc_enable_0
ad_connect axi_ad9652_adc_fifo/dout_data_0 data_pack/adc_data_0
ad_connect axi_ad9652_adc_fifo/dout_valid_1 data_pack/adc_valid_1
ad_connect axi_ad9652_adc_fifo/dout_enable_1 data_pack/adc_enable_1
ad_connect axi_ad9652_adc_fifo/dout_data_1 data_pack/adc_data_1
ad_connect axi_ad9652_adc_fifo/din_ovf axi_ad9652/adc_dovf
ad_connect data_pack/adc_valid axi_ad9652_dma/fifo_wr_en
ad_connect data_pack/adc_sync axi_ad9652_dma/fifo_wr_sync
ad_connect data_pack/adc_data axi_ad9652_dma/fifo_wr_din
ad_connect axi_ad9652_adc_fifo/dout_ovf axi_ad9652_dma/fifo_wr_overflow
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
ad_cpu_interconnect 0x79020000 axi_ad9652
ad_cpu_interconnect 0x7c420000 axi_ad9652_dma
# interconnect (mem/adc)
ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_200m_clk axi_ad9652_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad9652_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad9652_dma/irq