2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2020-06-19 07:52:10 +00:00
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# create debug ports
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create_bd_port -dir O adc1_div_clk
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create_bd_port -dir O adc2_div_clk
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create_bd_port -dir O dac1_div_clk
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create_bd_port -dir O dac2_div_clk
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2020-06-02 16:56:17 +00:00
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create_bd_port -dir I ref_clk
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create_bd_port -dir I tx_output_enable
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create_bd_port -dir I mssi_sync
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# adrv9001 interface
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create_bd_port -dir I rx1_dclk_in_n
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create_bd_port -dir I rx1_dclk_in_p
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create_bd_port -dir I rx1_idata_in_n
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create_bd_port -dir I rx1_idata_in_p
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create_bd_port -dir I rx1_qdata_in_n
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create_bd_port -dir I rx1_qdata_in_p
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create_bd_port -dir I rx1_strobe_in_n
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create_bd_port -dir I rx1_strobe_in_p
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create_bd_port -dir I rx2_dclk_in_n
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create_bd_port -dir I rx2_dclk_in_p
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create_bd_port -dir I rx2_idata_in_n
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create_bd_port -dir I rx2_idata_in_p
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create_bd_port -dir I rx2_qdata_in_n
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create_bd_port -dir I rx2_qdata_in_p
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create_bd_port -dir I rx2_strobe_in_n
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create_bd_port -dir I rx2_strobe_in_p
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create_bd_port -dir O tx1_dclk_out_n
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create_bd_port -dir O tx1_dclk_out_p
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create_bd_port -dir I tx1_dclk_in_n
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create_bd_port -dir I tx1_dclk_in_p
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create_bd_port -dir O tx1_idata_out_n
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create_bd_port -dir O tx1_idata_out_p
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create_bd_port -dir O tx1_qdata_out_n
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create_bd_port -dir O tx1_qdata_out_p
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create_bd_port -dir O tx1_strobe_out_n
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create_bd_port -dir O tx1_strobe_out_p
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create_bd_port -dir O tx2_dclk_out_n
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create_bd_port -dir O tx2_dclk_out_p
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create_bd_port -dir I tx2_dclk_in_n
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create_bd_port -dir I tx2_dclk_in_p
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create_bd_port -dir O tx2_idata_out_n
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create_bd_port -dir O tx2_idata_out_p
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create_bd_port -dir O tx2_qdata_out_n
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create_bd_port -dir O tx2_qdata_out_p
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create_bd_port -dir O tx2_strobe_out_n
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create_bd_port -dir O tx2_strobe_out_p
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2020-08-24 10:35:44 +00:00
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create_bd_port -dir O rx1_enable
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create_bd_port -dir O rx2_enable
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create_bd_port -dir O tx1_enable
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create_bd_port -dir O tx2_enable
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create_bd_port -dir I gpio_rx1_enable_in
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create_bd_port -dir I gpio_rx2_enable_in
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create_bd_port -dir I gpio_tx1_enable_in
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create_bd_port -dir I gpio_tx2_enable_in
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2020-09-11 12:13:23 +00:00
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create_bd_port -dir I tdd_sync
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create_bd_port -dir O tdd_sync_cntr
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2020-06-02 16:56:17 +00:00
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# adrv9001
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ad_ip_instance axi_adrv9001 axi_adrv9001
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ad_ip_parameter axi_adrv9001 CONFIG.CMOS_LVDS_N $ad_project_params(CMOS_LVDS_N)
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# dma for rx1
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ad_ip_instance axi_dmac axi_adrv9001_rx1_dma
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_instance util_cpack2 util_adc_1_pack { \
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NUM_OF_CHANNELS 4 \
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SAMPLE_DATA_WIDTH 16 \
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}
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# dma for rx2
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ad_ip_instance axi_dmac axi_adrv9001_rx2_dma
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_instance util_cpack2 util_adc_2_pack { \
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NUM_OF_CHANNELS 2 \
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SAMPLE_DATA_WIDTH 16 \
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}
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# dma for tx1
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ad_ip_instance axi_dmac axi_adrv9001_tx1_dma
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_instance util_upack2 util_dac_1_upack { \
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NUM_OF_CHANNELS 4 \
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SAMPLE_DATA_WIDTH 16 \
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}
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# dma for tx1
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ad_ip_instance axi_dmac axi_adrv9001_tx2_dma
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32
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ad_ip_instance util_upack2 util_dac_2_upack { \
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NUM_OF_CHANNELS 2 \
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SAMPLE_DATA_WIDTH 16 \
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}
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# ad9001 connections
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ad_connect $sys_iodelay_clk axi_adrv9001/delay_clk
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ad_connect axi_adrv9001/adc_1_clk axi_adrv9001_rx1_dma/fifo_wr_clk
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ad_connect axi_adrv9001/adc_1_clk util_adc_1_pack/clk
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ad_connect axi_adrv9001/adc_2_clk axi_adrv9001_rx2_dma/fifo_wr_clk
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ad_connect axi_adrv9001/adc_2_clk util_adc_2_pack/clk
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ad_connect axi_adrv9001/dac_1_clk axi_adrv9001_tx1_dma/m_axis_aclk
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ad_connect axi_adrv9001/dac_1_clk util_dac_1_upack/clk
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ad_connect axi_adrv9001/dac_2_clk axi_adrv9001_tx2_dma/m_axis_aclk
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ad_connect axi_adrv9001/dac_2_clk util_dac_2_upack/clk
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ad_connect ref_clk axi_adrv9001/ref_clk
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ad_connect tx_output_enable axi_adrv9001/tx_output_enable
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ad_connect mssi_sync axi_adrv9001/mssi_sync
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ad_connect rx1_dclk_in_n axi_adrv9001/rx1_dclk_in_n_NC
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ad_connect rx1_dclk_in_p axi_adrv9001/rx1_dclk_in_p_dclk_in
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ad_connect rx1_idata_in_n axi_adrv9001/rx1_idata_in_n_idata0
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ad_connect rx1_idata_in_p axi_adrv9001/rx1_idata_in_p_idata1
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ad_connect rx1_qdata_in_n axi_adrv9001/rx1_qdata_in_n_qdata2
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ad_connect rx1_qdata_in_p axi_adrv9001/rx1_qdata_in_p_qdata3
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ad_connect rx1_strobe_in_n axi_adrv9001/rx1_strobe_in_n_NC
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ad_connect rx1_strobe_in_p axi_adrv9001/rx1_strobe_in_p_strobe_in
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ad_connect rx2_dclk_in_n axi_adrv9001/rx2_dclk_in_n_NC
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ad_connect rx2_dclk_in_p axi_adrv9001/rx2_dclk_in_p_dclk_in
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ad_connect rx2_idata_in_n axi_adrv9001/rx2_idata_in_n_idata0
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ad_connect rx2_idata_in_p axi_adrv9001/rx2_idata_in_p_idata1
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ad_connect rx2_qdata_in_n axi_adrv9001/rx2_qdata_in_n_qdata2
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ad_connect rx2_qdata_in_p axi_adrv9001/rx2_qdata_in_p_qdata3
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ad_connect rx2_strobe_in_n axi_adrv9001/rx2_strobe_in_n_NC
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ad_connect rx2_strobe_in_p axi_adrv9001/rx2_strobe_in_p_strobe_in
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ad_connect tx1_dclk_out_n axi_adrv9001/tx1_dclk_out_n_NC
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ad_connect tx1_dclk_out_p axi_adrv9001/tx1_dclk_out_p_dclk_out
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ad_connect tx1_dclk_in_n axi_adrv9001/tx1_dclk_in_n_NC
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ad_connect tx1_dclk_in_p axi_adrv9001/tx1_dclk_in_p_dclk_in
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ad_connect tx1_idata_out_n axi_adrv9001/tx1_idata_out_n_idata0
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ad_connect tx1_idata_out_p axi_adrv9001/tx1_idata_out_p_idata1
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ad_connect tx1_qdata_out_n axi_adrv9001/tx1_qdata_out_n_qdata2
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ad_connect tx1_qdata_out_p axi_adrv9001/tx1_qdata_out_p_qdata3
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ad_connect tx1_strobe_out_n axi_adrv9001/tx1_strobe_out_n_NC
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ad_connect tx1_strobe_out_p axi_adrv9001/tx1_strobe_out_p_strobe_out
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ad_connect tx2_dclk_out_n axi_adrv9001/tx2_dclk_out_n_NC
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ad_connect tx2_dclk_out_p axi_adrv9001/tx2_dclk_out_p_dclk_out
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ad_connect tx2_dclk_in_n axi_adrv9001/tx2_dclk_in_n_NC
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ad_connect tx2_dclk_in_p axi_adrv9001/tx2_dclk_in_p_dclk_in
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ad_connect tx2_idata_out_n axi_adrv9001/tx2_idata_out_n_idata0
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ad_connect tx2_idata_out_p axi_adrv9001/tx2_idata_out_p_idata1
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ad_connect tx2_qdata_out_n axi_adrv9001/tx2_qdata_out_n_qdata2
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ad_connect tx2_qdata_out_p axi_adrv9001/tx2_qdata_out_p_qdata3
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ad_connect tx2_strobe_out_n axi_adrv9001/tx2_strobe_out_n_NC
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ad_connect tx2_strobe_out_p axi_adrv9001/tx2_strobe_out_p_strobe_out
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2020-08-24 10:35:44 +00:00
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ad_connect rx1_enable axi_adrv9001/rx1_enable
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ad_connect rx2_enable axi_adrv9001/rx2_enable
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ad_connect tx1_enable axi_adrv9001/tx1_enable
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ad_connect tx2_enable axi_adrv9001/tx2_enable
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ad_connect gpio_rx1_enable_in axi_adrv9001/gpio_rx1_enable_in
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ad_connect gpio_rx2_enable_in axi_adrv9001/gpio_rx2_enable_in
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ad_connect gpio_tx1_enable_in axi_adrv9001/gpio_tx1_enable_in
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ad_connect gpio_tx2_enable_in axi_adrv9001/gpio_tx2_enable_in
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2020-09-11 12:13:23 +00:00
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ad_connect tdd_sync axi_adrv9001/tdd_sync
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ad_connect tdd_sync_cntr axi_adrv9001/tdd_sync_cntr
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2020-06-02 16:56:17 +00:00
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# RX1_RX2 - CPACK - RX_DMA1
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ad_connect axi_adrv9001/adc_1_rst util_adc_1_pack/reset
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ad_connect axi_adrv9001/adc_1_valid_i0 util_adc_1_pack/fifo_wr_en
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ad_connect axi_adrv9001/adc_1_enable_i0 util_adc_1_pack/enable_0
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ad_connect axi_adrv9001/adc_1_data_i0 util_adc_1_pack/fifo_wr_data_0
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ad_connect axi_adrv9001/adc_1_enable_q0 util_adc_1_pack/enable_1
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ad_connect axi_adrv9001/adc_1_data_q0 util_adc_1_pack/fifo_wr_data_1
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ad_connect axi_adrv9001/adc_1_enable_i1 util_adc_1_pack/enable_2
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ad_connect axi_adrv9001/adc_1_data_i1 util_adc_1_pack/fifo_wr_data_2
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ad_connect axi_adrv9001/adc_1_enable_q1 util_adc_1_pack/enable_3
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ad_connect axi_adrv9001/adc_1_data_q1 util_adc_1_pack/fifo_wr_data_3
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ad_connect axi_adrv9001/adc_1_dovf util_adc_1_pack/fifo_wr_overflow
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ad_connect util_adc_1_pack/packed_fifo_wr axi_adrv9001_rx1_dma/fifo_wr
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# RX2 - CPACK - RX_DMA2
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ad_connect axi_adrv9001/adc_2_rst util_adc_2_pack/reset
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ad_connect axi_adrv9001/adc_2_valid_i0 util_adc_2_pack/fifo_wr_en
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ad_connect axi_adrv9001/adc_2_enable_i0 util_adc_2_pack/enable_0
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ad_connect axi_adrv9001/adc_2_data_i0 util_adc_2_pack/fifo_wr_data_0
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ad_connect axi_adrv9001/adc_2_enable_q0 util_adc_2_pack/enable_1
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ad_connect axi_adrv9001/adc_2_data_q0 util_adc_2_pack/fifo_wr_data_1
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ad_connect axi_adrv9001/adc_2_dovf util_adc_2_pack/fifo_wr_overflow
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ad_connect util_adc_2_pack/packed_fifo_wr axi_adrv9001_rx2_dma/fifo_wr
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# TX_DMA1 - UPACK - TX1
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ad_connect axi_adrv9001/dac_1_rst util_dac_1_upack/reset
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ad_connect axi_adrv9001/dac_1_valid_i0 util_dac_1_upack/fifo_rd_en
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ad_connect axi_adrv9001/dac_1_enable_i0 util_dac_1_upack/enable_0
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ad_connect axi_adrv9001/dac_1_data_i0 util_dac_1_upack/fifo_rd_data_0
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ad_connect axi_adrv9001/dac_1_enable_q0 util_dac_1_upack/enable_1
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ad_connect axi_adrv9001/dac_1_data_q0 util_dac_1_upack/fifo_rd_data_1
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ad_connect axi_adrv9001/dac_1_enable_i1 util_dac_1_upack/enable_2
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ad_connect axi_adrv9001/dac_1_data_i1 util_dac_1_upack/fifo_rd_data_2
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ad_connect axi_adrv9001/dac_1_enable_q1 util_dac_1_upack/enable_3
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ad_connect axi_adrv9001/dac_1_data_q1 util_dac_1_upack/fifo_rd_data_3
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ad_connect axi_adrv9001_tx1_dma/m_axis util_dac_1_upack/s_axis
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ad_connect axi_adrv9001/dac_1_dunf util_dac_1_upack/fifo_rd_underflow
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# TX_DMA2 - UPACK - TX2
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ad_connect axi_adrv9001/dac_2_rst util_dac_2_upack/reset
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ad_connect axi_adrv9001/dac_2_valid_i0 util_dac_2_upack/fifo_rd_en
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ad_connect axi_adrv9001/dac_2_enable_i0 util_dac_2_upack/enable_0
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ad_connect axi_adrv9001/dac_2_data_i0 util_dac_2_upack/fifo_rd_data_0
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ad_connect axi_adrv9001/dac_2_enable_q0 util_dac_2_upack/enable_1
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ad_connect axi_adrv9001/dac_2_data_q0 util_dac_2_upack/fifo_rd_data_1
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ad_connect axi_adrv9001_tx2_dma/m_axis util_dac_2_upack/s_axis
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ad_connect axi_adrv9001/dac_2_dunf util_dac_2_upack/fifo_rd_underflow
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# interconnect
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ad_cpu_interconnect 0x44A00000 axi_adrv9001
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ad_cpu_interconnect 0x44A30000 axi_adrv9001_rx1_dma
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ad_cpu_interconnect 0x44A40000 axi_adrv9001_rx2_dma
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ad_cpu_interconnect 0x44A50000 axi_adrv9001_tx1_dma
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ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma
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# memory inteconnect
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2020-08-24 14:25:52 +00:00
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi
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ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi
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ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi
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ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi
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ad_connect $sys_cpu_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn
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ad_connect $sys_cpu_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn
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ad_connect $sys_cpu_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn
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ad_connect $sys_cpu_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn
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2020-06-02 16:56:17 +00:00
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq
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ad_cpu_interrupt ps-12 mb-11 axi_adrv9001_rx2_dma/irq
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2022-02-16 13:14:53 +00:00
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ad_cpu_interrupt ps-9 mb-6 axi_adrv9001_tx1_dma/irq
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2020-06-02 16:56:17 +00:00
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ad_cpu_interrupt ps-10 mb-5 axi_adrv9001_tx2_dma/irq
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2020-06-19 07:52:10 +00:00
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# Connect debug ports
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ad_connect axi_adrv9001/adc_1_clk adc1_div_clk
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ad_connect axi_adrv9001/adc_2_clk adc2_div_clk
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ad_connect axi_adrv9001/dac_1_clk dac1_div_clk
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ad_connect axi_adrv9001/dac_2_clk dac2_div_clk
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