203 lines
6.8 KiB
Tcl
203 lines
6.8 KiB
Tcl
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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# system level parameters
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set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
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set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE)
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set CLK_MODE $ad_project_params(CLK_MODE)
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set DDR_EN $ad_project_params(DDR_EN)
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puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN"
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# block design ports and interfaces
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# specify the CNV generator's reference clock frequency in MHz
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# NOTE: this is a default value, software may or may not change this
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set cnv_ref_clk 100
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# specify ADC sampling rate in samples/seconds
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# NOTE: this is a default value, software may or may not change this
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set adc_sampling_rate 1000000
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#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_spi
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create_bd_port -dir O ad463x_spi_sclk
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create_bd_port -dir O ad463x_spi_cs
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create_bd_port -dir O ad463x_spi_sdo
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create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_spi_sdi
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create_bd_port -dir I ad463x_echo_sclk
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create_bd_port -dir I ad463x_busy
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create_bd_port -dir O ad463x_cnv
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create_bd_port -dir I ad463x_ext_clk
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## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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# create a SPI Engine architecture
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###
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# name data_width async_spi_clk num_csn num_sdi sdi_delay echo_sclk
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spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1
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ad_ip_parameter spi_ad463x/execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_3 $DDR_EN
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## to setup the sample rate of the system change the PULSE_PERIOD value of the
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## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
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set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
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ad_ip_instance axi_pwm_gen cnv_generator
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ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
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ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
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ad_ip_parameter cnv_generator CONFIG.PULSE_0_WIDTH 1
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1
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ad_ip_instance spi_axis_reorder data_reorder
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ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad463x_dma
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad463x_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# Trigger for SPI offload
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if {$CAPTURE_ZONE == 1} {
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## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
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# is used for SDI latching
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switch $CLK_MODE {
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0 {
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ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk
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}
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1 -
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2 {
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puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 1)."
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exit 2
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}
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default {
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puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)"
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exit 2
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}
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}
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# Zone 1 - trigger to BUSY's negative edge
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect spi_clk busy_capture/clk
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ad_connect spi_clk busy_sync/out_clk
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ad_connect busy_capture/rst GND
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ad_connect spi_ad463x/axi_regmap/spi_resetn busy_sync/out_resetn
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ad_connect ad463x_busy busy_sync/in_bits
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ad_connect busy_sync/out_bits busy_capture/signal_in
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ad_connect busy_capture/signal_out spi_ad463x/trigger
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## SDI is latched by the SPIE execution module
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ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis
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} elseif {$CAPTURE_ZONE == 2} {
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# Zone 2 - trigger to next consecutive CNV
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ad_ip_parameter spi_ad463x/offload CONFIG.ASYNC_TRIG 1
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ad_connect cnv_generator/pwm_0 spi_ad463x/trigger
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## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
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# is used for SDI latching
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ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk
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switch $CLK_MODE {
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0 {
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## SDI is latched by the SPIE execution module
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ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis
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}
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1 -
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2 {
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## SDI is latched by the data capture
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ad_ip_instance ad463x_data_capture data_capture
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ad_ip_parameter data_capture CONFIG.DDR_EN $DDR_EN
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ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI
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ad_connect spi_clk data_capture/clk
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ad_connect ad463x_spi_cs data_capture/csn
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ad_connect ad463x_busy data_capture/echo_sclk
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ad_connect ad463x_spi_sdi data_capture/data_in
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ad_connect data_capture/m_axis data_reorder/s_axis
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}
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default {
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puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)"
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exit 2
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}
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}
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} else {
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puts "ERROR: Invalid capture zone, please choose 1 or 2."
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exit 2
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}
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ad_connect ad463x_cnv cnv_generator/pwm_1
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# clocks
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ad_connect $sys_cpu_clk spi_ad463x/clk
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ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
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ad_connect spi_clk spi_ad463x/spi_clk
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ad_connect spi_clk data_reorder/axis_aclk
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ad_connect spi_clk axi_ad463x_dma/s_axis_aclk
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ad_connect ad463x_ext_clk cnv_generator/ext_clk
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# resets
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ad_connect $sys_cpu_resetn cnv_generator/s_axi_aresetn
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ad_connect data_reorder/axis_aresetn VCC
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ad_connect $sys_cpu_resetn spi_ad463x/resetn
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ad_connect $sys_cpu_resetn axi_ad463x_dma/m_dest_axi_aresetn
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# data path
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ad_connect spi_ad463x/execution/cs ad463x_spi_cs
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ad_connect spi_ad463x/execution/sclk ad463x_spi_sclk
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ad_connect spi_ad463x/execution/sdo ad463x_spi_sdo
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ad_connect spi_ad463x/execution/sdi ad463x_spi_sdi
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ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis
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# AXI memory mapped address space
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ad_cpu_interconnect 0x44a00000 spi_ad463x/axi_regmap
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ad_cpu_interconnect 0x44b00000 cnv_generator
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ad_cpu_interconnect 0x44a30000 axi_ad463x_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad463x_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi_ad463x/irq
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# interconnect to memory interface
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi
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