pluto_hdl_adi/library/axi_ad9361/axi_ad9361_tx_channel.v

// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
// All rights reserved.
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// are permitted provided that the following conditions are met:
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//     - Use of the software either in source or binary form, must be run
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module axi_ad9361_tx_channel (

  // dac interface

  dac_clk,
  dac_rst,
  dac_dds_data,

  // processor interface

  dac_dds_enable,
  dac_dds_data_enable,
  dac_dds_format,
  dac_dds_pattenb,
  dac_lb_enb,
  dac_pn_enb,

  // bus interface

  up_rstn,
  up_clk,
  up_sel,
  up_wr,
  up_addr,
  up_wdata,
  up_rdata,
  up_ack);

  // parameters

  parameter CHID = 32'h0;
  parameter DP_DISABLE = 0;

  // dac interface

  input           dac_clk;
  input           dac_rst;
  output  [15:0]  dac_dds_data;

  // processor interface

  input           dac_dds_enable;
  input           dac_dds_data_enable;
  input           dac_dds_format;
  input           dac_dds_pattenb;
  output          dac_lb_enb;
  output          dac_pn_enb;

  // bus interface

  input           up_rstn;
  input           up_clk;
  input           up_sel;
  input           up_wr;
  input   [13:0]  up_addr;
  input   [31:0]  up_wdata;
  output  [31:0]  up_rdata;
  output          up_ack;

  // internal signals

  wire    [15:0]  dac_dds_patt_1_s;
  wire    [15:0]  dac_dds_init_1_s;
  wire    [15:0]  dac_dds_incr_1_s;
  wire    [15:0]  dac_dds_scale_1_s;
  wire    [15:0]  dac_dds_patt_2_s;
  wire    [15:0]  dac_dds_init_2_s;
  wire    [15:0]  dac_dds_incr_2_s;
  wire    [15:0]  dac_dds_scale_2_s;

  // single channel dds

  axi_ad9361_tx_dds #(.DP_DISABLE(DP_DISABLE)) i_tx_dds (
    .dac_clk (dac_clk),
    .dac_rst (dac_rst),
    .dac_dds_data (dac_dds_data),
    .dac_dds_enable (dac_dds_enable),
    .dac_dds_data_enable (dac_dds_data_enable),
    .dac_dds_format (dac_dds_format),
    .dac_dds_pattenb (dac_dds_pattenb),
    .dac_dds_patt_1 (dac_dds_patt_1_s),
    .dac_dds_init_1 (dac_dds_init_1_s),
    .dac_dds_incr_1 (dac_dds_incr_1_s),
    .dac_dds_scale_1 (dac_dds_scale_1_s),
    .dac_dds_patt_2 (dac_dds_patt_2_s),
    .dac_dds_init_2 (dac_dds_init_2_s),
    .dac_dds_incr_2 (dac_dds_incr_2_s),
    .dac_dds_scale_2 (dac_dds_scale_2_s));

  // single channel processor

  up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
    .dac_clk (dac_clk),
    .dac_rst (dac_rst),
    .dac_dds_scale_1 (dac_dds_scale_1_s),
    .dac_dds_init_1 (dac_dds_init_1_s),
    .dac_dds_incr_1 (dac_dds_incr_1_s),
    .dac_dds_scale_2 (dac_dds_scale_2_s),
    .dac_dds_init_2 (dac_dds_init_2_s),
    .dac_dds_incr_2 (dac_dds_incr_2_s),
    .dac_dds_patt_1 (dac_dds_patt_1_s),
    .dac_dds_patt_2 (dac_dds_patt_2_s),
    .dac_dds_sel (),
    .dac_lb_enb (dac_lb_enb),
    .dac_pn_enb (dac_pn_enb),
    .up_usr_datatype_be (),
    .up_usr_datatype_signed (),
    .up_usr_datatype_shift (),
    .up_usr_datatype_total_bits (),
    .up_usr_datatype_bits (),
    .up_usr_interpolation_m (),
    .up_usr_interpolation_n (),
    .dac_usr_datatype_be (1'b0),
    .dac_usr_datatype_signed (1'b1),
    .dac_usr_datatype_shift (8'd0),
    .dac_usr_datatype_total_bits (8'd16),
    .dac_usr_datatype_bits (8'd16),
    .dac_usr_interpolation_m (16'd1),
    .dac_usr_interpolation_n (16'd1),
    .up_rstn (up_rstn),
    .up_clk (up_clk),
    .up_sel (up_sel),
    .up_wr (up_wr),
    .up_addr (up_addr),
    .up_wdata (up_wdata),
    .up_rdata (up_rdata),
    .up_ack (up_ack));
  
endmodule

// ***************************************************************************
// ***************************************************************************