318 lines
10 KiB
Coq
318 lines
10 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_fifo2s_rd (
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// request and synchronization
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axi_xfer_req,
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axi_rd_req,
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axi_rd_addr,
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axi_rd_status,
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// axi interface
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axi_clk,
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axi_resetn,
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axi_arvalid,
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axi_arid,
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axi_arburst,
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axi_arlock,
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axi_arcache,
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axi_arprot,
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axi_arqos,
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axi_aruser,
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axi_arlen,
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axi_arsize,
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axi_araddr,
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axi_arready,
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axi_rvalid,
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axi_rid,
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axi_ruser,
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axi_rresp,
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axi_rlast,
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axi_rdata,
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axi_rready,
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// fifo interface
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axi_mwr,
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axi_mwdata,
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axi_mwovf,
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axi_mwpfull);
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// parameters
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parameter DATA_WIDTH = 32;
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parameter AXI_SIZE = 2;
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parameter AXI_LENGTH = 16;
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localparam BUF_THRESHOLD_LO = 6'd3;
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localparam BUF_THRESHOLD_HI = 6'd60;
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// request and synchronization
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input axi_xfer_req;
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input axi_rd_req;
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input [ 31:0] axi_rd_addr;
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output axi_rd_status;
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// axi interface
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input axi_clk;
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input axi_resetn;
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output axi_arvalid;
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output [ 3:0] axi_arid;
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output [ 1:0] axi_arburst;
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output axi_arlock;
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output [ 3:0] axi_arcache;
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output [ 2:0] axi_arprot;
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output [ 3:0] axi_arqos;
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output [ 3:0] axi_aruser;
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output [ 7:0] axi_arlen;
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output [ 2:0] axi_arsize;
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output [ 31:0] axi_araddr;
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input axi_arready;
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input axi_rvalid;
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input [ 3:0] axi_rid;
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input [ 3:0] axi_ruser;
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input [ 1:0] axi_rresp;
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input axi_rlast;
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input [DATA_WIDTH-1:0] axi_rdata;
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output axi_rready;
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// fifo interface
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output axi_mwr;
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output [DATA_WIDTH-1:0] axi_mwdata;
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input axi_mwovf;
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input axi_mwpfull;
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// internal registers
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reg [ 5:0] axi_waddr = 'd0;
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reg [ 5:0] axi_raddr = 'd0;
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reg axi_rd = 'd0;
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reg axi_rd_d = 'd0;
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reg [ 31:0] axi_rdata_d = 'd0;
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reg [ 5:0] axi_addr_diff = 'd0;
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reg axi_almost_full = 'd0;
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reg axi_unf = 'd0;
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reg axi_almost_empty = 'd0;
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reg axi_ovf = 'd0;
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reg axi_arerror = 'd0;
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reg axi_arvalid = 'd0;
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reg [ 31:0] axi_araddr = 'd0;
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reg axi_mwr = 'd0;
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reg [DATA_WIDTH-1:0] axi_mwdata = 'd0;
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reg axi_rready = 'd0;
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reg axi_rerror = 'd0;
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reg axi_reset = 'd0;
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reg axi_rd_status = 'd0;
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// internal signals
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wire axi_wr_s;
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wire [ 31:0] axi_wdata_s;
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wire axi_arready_s;
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wire axi_fifo_ready_s;
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wire axi_rd_s;
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wire [ 6:0] axi_addr_diff_s;
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wire [ 31:0] axi_rdata_s;
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// queue requests
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assign axi_wr_s = axi_rd_req;
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assign axi_wdata_s = axi_rd_addr;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_waddr <= 'd0;
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end else begin
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if (axi_wr_s == 1'b1) begin
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axi_waddr <= axi_waddr + 1'b1;
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end
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end
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end
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// read queue
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assign axi_arready_s = ~axi_arvalid | axi_arready;
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assign axi_fifo_ready_s = ~axi_xfer_req | ~axi_mwpfull;
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assign axi_rd_s = (axi_waddr == axi_raddr) ? 1'b0 : (axi_arready_s & axi_fifo_ready_s);
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_raddr <= 'd0;
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axi_rd <= 'd0;
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axi_rd_d <= 'd0;
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axi_rdata_d <= 'd0;
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end else begin
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if (axi_rd_s == 1'b1) begin
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axi_raddr <= axi_raddr + 1'b1;
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end
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axi_rd <= axi_rd_s;
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axi_rd_d <= axi_rd;
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axi_rdata_d <= axi_rdata_s;
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end
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end
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// overflow (no underflow possible)
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assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_addr_diff <= 'd0;
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axi_almost_full <= 'd0;
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axi_unf <= 'd0;
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axi_almost_empty <= 'd0;
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axi_ovf <= 'd0;
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end else begin
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axi_addr_diff <= axi_addr_diff_s[5:0];
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if (axi_addr_diff > BUF_THRESHOLD_HI) begin
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axi_almost_full <= 1'b1;
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axi_unf <= axi_almost_empty;
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end else begin
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axi_almost_full <= 1'b0;
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axi_unf <= 1'b0;
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end
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if (axi_addr_diff < BUF_THRESHOLD_LO) begin
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axi_almost_empty <= 1'b1;
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axi_ovf <= axi_almost_full;
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end else begin
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axi_almost_empty <= 1'b0;
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axi_ovf <= 1'b0;
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end
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end
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end
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// address channel
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assign axi_arid = 4'b0000;
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assign axi_arburst = 2'b01;
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assign axi_arlock = 1'b0;
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assign axi_arcache = 4'b0010;
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assign axi_arprot = 3'b000;
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assign axi_arqos = 4'b0000;
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assign axi_aruser = 4'b0001;
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assign axi_arlen = AXI_LENGTH - 1;
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assign axi_arsize = AXI_SIZE;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_arerror <= 'd0;
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axi_arvalid <= 'd0;
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axi_araddr <= 'd0;
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end else begin
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axi_arerror <= axi_rd_d & axi_arvalid;
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if (axi_arvalid == 1'b1) begin
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if (axi_arready == 1'b1) begin
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axi_arvalid <= 1'b0;
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end
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end else begin
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if (axi_rd_d == 1'b1) begin
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axi_arvalid <= 1'b1;
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end
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end
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if ((axi_rd_d == 1'b1) && (axi_arvalid == 1'b0)) begin
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axi_araddr <= axi_rdata_d;
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end
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end
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end
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// read data channel
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_mwr <= 'd0;
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axi_mwdata <= 'd0;
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axi_rready <= 'd0;
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end else begin
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axi_mwr <= axi_rvalid & axi_rready;
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axi_mwdata <= axi_rdata;
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axi_rready <= axi_fifo_ready_s;
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end
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end
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_rerror <= 'd0;
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end else begin
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axi_rerror <= axi_rvalid & axi_rready & axi_rresp[1];
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end
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end
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// fifo needs a reset
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_reset <= 1'b1;
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end else begin
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axi_reset <= 1'b0;
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end
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end
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// combined status
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_rd_status <= 'd0;
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end else begin
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axi_rd_status <= axi_mwovf | axi_ovf | axi_unf | axi_arerror | axi_rerror;
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end
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end
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// buffer
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ad_mem #(.DATA_WIDTH(32), .ADDR_WIDTH(6)) i_mem (
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.clka (axi_clk),
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.wea (axi_wr_s),
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.addra (axi_waddr),
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.dina (axi_wdata_s),
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.clkb (axi_clk),
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.addrb (axi_raddr),
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.doutb (axi_rdata_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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