2016-05-03 19:59:20 +00:00
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# create board design
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# default ports
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2016-05-10 19:40:32 +00:00
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create_bd_port -dir O -from 2 -to 0 spi0_csn
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create_bd_port -dir O spi0_sclk
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create_bd_port -dir O spi0_mosi
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create_bd_port -dir I spi0_miso
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create_bd_port -dir O -from 2 -to 0 spi1_csn
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create_bd_port -dir O spi1_sclk
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create_bd_port -dir O spi1_mosi
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create_bd_port -dir I spi1_miso
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2016-10-05 18:01:59 +00:00
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create_bd_port -dir I -from 94 -to 0 gpio_i
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create_bd_port -dir O -from 94 -to 0 gpio_o
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2016-05-03 19:59:20 +00:00
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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2016-05-10 19:40:32 +00:00
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create_bd_port -dir I -type intr ps_intr_14
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create_bd_port -dir I -type intr ps_intr_15
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# instance: sys_ps8
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2017-05-02 09:30:00 +00:00
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ad_ip_instance zynq_ultra_ps_e sys_ps8
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2017-05-18 18:17:20 +00:00
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apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e \
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-config {apply_board_preset 1} [get_bd_cells sys_ps8]
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2016-05-10 19:40:32 +00:00
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2017-05-18 18:17:20 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
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2017-05-02 09:52:43 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
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2017-05-18 18:17:20 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 100
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2017-05-02 09:52:43 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
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2017-05-18 18:17:20 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
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2017-05-02 09:52:43 +00:00
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 200
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
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2016-05-10 19:40:32 +00:00
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2017-05-18 18:17:20 +00:00
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set_property -dict [list \
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CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
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2016-05-10 19:40:32 +00:00
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CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
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2017-05-18 18:17:20 +00:00
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CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
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CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
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CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
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CONFIG.PSU__SPI1__PERIPHERAL__ENABLE 1 \
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CONFIG.PSU__SPI1__PERIPHERAL__IO EMIO \
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CONFIG.PSU__SPI1__GRP_SS1__ENABLE 1 \
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CONFIG.PSU__SPI1__GRP_SS2__ENABLE 1 \
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CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ 100 \
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2017-05-02 09:30:00 +00:00
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] [get_bd_cells sys_ps8]
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2016-10-05 18:01:59 +00:00
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2017-05-02 09:30:00 +00:00
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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2016-05-03 19:59:20 +00:00
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2016-05-10 19:40:32 +00:00
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps8/pl_clk0
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ad_connect sys_200m_clk sys_ps8/pl_clk1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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2016-10-06 14:18:02 +00:00
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ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
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2016-05-03 19:59:20 +00:00
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2016-05-10 19:40:32 +00:00
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# gpio
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2016-05-03 19:59:20 +00:00
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2016-05-10 19:40:32 +00:00
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ad_connect gpio_i sys_ps8/emio_gpio_i
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ad_connect gpio_o sys_ps8/emio_gpio_o
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2016-05-03 19:59:20 +00:00
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2016-05-10 19:40:32 +00:00
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# spi
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2016-05-03 19:59:20 +00:00
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2017-07-21 08:22:10 +00:00
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ad_ip_instance xlconcat spi0_csn_concat
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ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
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ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
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ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
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ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
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ad_connect spi0_csn_concat/dout spi0_csn
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2016-10-05 18:01:59 +00:00
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ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
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ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
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ad_connect sys_ps8/emio_spi0_m_i spi0_miso
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2016-05-10 19:40:32 +00:00
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ad_connect sys_ps8/emio_spi0_ss_i_n VCC
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2016-10-05 18:01:59 +00:00
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ad_connect sys_ps8/emio_spi0_sclk_i GND
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ad_connect sys_ps8/emio_spi0_s_i GND
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2016-05-03 19:59:20 +00:00
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2017-07-21 08:22:10 +00:00
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ad_ip_instance xlconcat spi1_csn_concat
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ad_ip_parameter spi1_csn_concat CONFIG.NUM_PORTS 3
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ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn_concat/In0
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ad_connect sys_ps8/emio_spi1_ss1_o_n spi1_csn_concat/In1
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ad_connect sys_ps8/emio_spi1_ss2_o_n spi1_csn_concat/In2
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ad_connect spi1_csn_concat/dout spi1_csn
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2016-10-05 18:01:59 +00:00
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ad_connect sys_ps8/emio_spi1_sclk_o spi1_sclk
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ad_connect sys_ps8/emio_spi1_m_o spi1_mosi
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ad_connect sys_ps8/emio_spi1_m_i spi1_miso
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2016-05-10 19:40:32 +00:00
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ad_connect sys_ps8/emio_spi1_ss_i_n VCC
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2016-10-05 18:01:59 +00:00
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ad_connect sys_ps8/emio_spi1_sclk_i GND
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ad_connect sys_ps8/emio_spi1_s_i GND
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2016-05-03 19:59:20 +00:00
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# interrupts
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2017-05-02 09:30:00 +00:00
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ad_ip_instance xlconcat sys_concat_intc_0
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ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
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2016-05-10 19:40:32 +00:00
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2017-05-02 09:30:00 +00:00
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ad_ip_instance xlconcat sys_concat_intc_1
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ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
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2016-05-10 19:40:32 +00:00
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ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
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ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
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ad_connect sys_concat_intc_1/In7 ps_intr_15
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ad_connect sys_concat_intc_1/In6 ps_intr_14
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ad_connect sys_concat_intc_1/In5 ps_intr_13
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ad_connect sys_concat_intc_1/In4 ps_intr_12
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ad_connect sys_concat_intc_1/In3 ps_intr_11
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ad_connect sys_concat_intc_1/In2 ps_intr_10
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ad_connect sys_concat_intc_1/In1 ps_intr_09
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ad_connect sys_concat_intc_1/In0 ps_intr_08
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ad_connect sys_concat_intc_0/In7 ps_intr_07
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ad_connect sys_concat_intc_0/In6 ps_intr_06
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ad_connect sys_concat_intc_0/In5 ps_intr_05
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ad_connect sys_concat_intc_0/In4 ps_intr_04
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ad_connect sys_concat_intc_0/In3 ps_intr_03
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ad_connect sys_concat_intc_0/In2 ps_intr_02
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ad_connect sys_concat_intc_0/In1 ps_intr_01
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ad_connect sys_concat_intc_0/In0 ps_intr_00
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2016-05-03 19:59:20 +00:00
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