zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/util_rfifo/util_rfifo_constr.xdc

11 lines
889 B
Plaintext
Raw Normal View History

util_rfifo: constraints
2016-05-16 14:45:33 +00:00
constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.
2017-02-24 11:43:32 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_unf_m*}]
util_rfifo: constraints
2016-05-16 14:45:33 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dout_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1* && IS_SEQUENTIAL}]
rfifo- buffer 1 seg before read
2016-07-12 14:24:02 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dout_rinit* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_rinit* && IS_SEQUENTIAL}]
util_rfifo: constraints
2016-05-16 14:45:33 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *din_unf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1* && IS_SEQUENTIAL}]