2014-04-01 15:46:37 +00:00
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2016-11-10 21:57:06 +00:00
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create_clock -period "10.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}]
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create_clock -period "8.000 ns" -name eth_rx_clk [get_ports {eth_rx_clk}]
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2014-04-01 15:46:37 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2015-06-25 08:25:39 +00:00
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set_clock_groups -exclusive \
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2016-11-10 21:57:06 +00:00
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
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2016-12-22 19:13:14 +00:00
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set_false_path -to [get_registers *sysref_en_m1*]
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2016-11-10 21:57:06 +00:00
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2016-12-22 19:13:14 +00:00
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set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \
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2016-11-10 21:57:06 +00:00
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-to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
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2016-12-22 19:13:14 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
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-through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
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2016-11-10 21:57:06 +00:00
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2016-12-22 19:13:14 +00:00
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set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
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2016-11-10 21:57:06 +00:00
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-to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
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2016-12-22 19:13:14 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
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-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
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2016-11-10 21:57:06 +00:00
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2017-01-04 19:10:44 +00:00
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set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
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-to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2
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