2016-10-24 07:59:07 +00:00
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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ifeq ($(MMU),)
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MMU := 1
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endif
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export ALT_NIOS_MMU_ENABLED := $(MMU)
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M_DEPS += system_top.v
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M_DEPS += system_qsys.tcl
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.sdc
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../common/daq1_spi.v
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../common/daq1_qsys.tcl
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../scripts/adi_tquest.tcl
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../scripts/adi_env.tcl
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../common/altera/sys_gen.tcl
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
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2017-03-20 20:05:18 +00:00
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M_DEPS += ../../../library/altera/common/ad_mem_asym.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/altera/common/ad_mul.v
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122_constr.sdc
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
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M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684_constr.sdc
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v
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M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v
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M_DEPS += ../../../library/axi_dmac/2d_transfer.v
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M_DEPS += ../../../library/axi_dmac/address_generator.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
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M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
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M_DEPS += ../../../library/axi_dmac/data_mover.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
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M_DEPS += ../../../library/axi_dmac/inc_id.h
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M_DEPS += ../../../library/axi_dmac/request_arb.v
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M_DEPS += ../../../library/axi_dmac/request_generator.v
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M_DEPS += ../../../library/axi_dmac/resp.h
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M_DEPS += ../../../library/axi_dmac/response_generator.v
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M_DEPS += ../../../library/axi_dmac/response_handler.v
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M_DEPS += ../../../library/axi_dmac/splitter.v
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M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
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2016-10-31 19:45:26 +00:00
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M_DEPS += ../../../library/common/ad_axis_inf_rx.v
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/common/ad_datafmt.v
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M_DEPS += ../../../library/common/ad_dds.v
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M_DEPS += ../../../library/common/ad_dds_1.v
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M_DEPS += ../../../library/common/ad_dds_sine.v
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M_DEPS += ../../../library/common/ad_pnmon.v
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M_DEPS += ../../../library/common/ad_rst.v
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M_DEPS += ../../../library/common/sync_bits.v
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M_DEPS += ../../../library/common/sync_gray.v
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M_DEPS += ../../../library/common/up_adc_channel.v
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M_DEPS += ../../../library/common/up_adc_common.v
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M_DEPS += ../../../library/common/up_axi.v
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M_DEPS += ../../../library/common/up_clock_mon.v
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M_DEPS += ../../../library/common/up_dac_channel.v
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M_DEPS += ../../../library/common/up_dac_common.v
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M_DEPS += ../../../library/common/up_delay_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_status.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/scripts/adi_env.tcl
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M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
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2016-10-31 19:45:26 +00:00
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
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2016-12-09 21:06:41 +00:00
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
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2016-10-31 19:45:26 +00:00
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
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2016-10-24 07:59:07 +00:00
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M_DEPS += ../../../library/util_axis_fifo/address_gray.v
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M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
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M_DEPS += ../../../library/util_axis_fifo/address_sync.v
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M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
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M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
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M_DEPS += ../../../library/util_cpack/util_cpack.v
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M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
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M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
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M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
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M_DEPS += ../../../library/util_upack/util_upack.v
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M_DEPS += ../../../library/util_upack/util_upack_dmx.v
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M_DEPS += ../../../library/util_upack/util_upack_dsf.v
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M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
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M_ALTERA := quartus_sh --64bit -t
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M_FLIST += *.log
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M_FLIST += *_INFO.txt
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M_FLIST += *_dump.txt
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M_FLIST += db
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M_FLIST += *.asm.rpt
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M_FLIST += *.done
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M_FLIST += *.eda.rpt
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M_FLIST += *.fit.*
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M_FLIST += *.map.*
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M_FLIST += *.sta.*
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M_FLIST += *.qsf
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M_FLIST += *.qpf
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M_FLIST += *.qws
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M_FLIST += *.sof
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M_FLIST += *.cdf
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M_FLIST += *.sld
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M_FLIST += *.qdf
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M_FLIST += hc_output
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M_FLIST += system_bd
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M_FLIST += hps_isw_handoff
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M_FLIST += hps_sdram_*.csv
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M_FLIST += *ddr3_*.csv
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M_FLIST += incremental_db
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M_FLIST += reconfig_mif
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M_FLIST += *.sopcinfo
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M_FLIST += *.jdi
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M_FLIST += *.pin
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M_FLIST += *_summary.csv
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M_FLIST += *.dpf
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.PHONY: all clean clean-all
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all: daq1_a10gx.sof
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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daq1_a10gx.sof: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_ALTERA) system_project.tcl >> daq1_a10gx_quartus.log 2>&1
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####################################################################################
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####################################################################################
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