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pluto_hdl_adi/projects/ad6676evb/common/ad6676evb_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc peripherals
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad6676_xcvr]
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr
set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr
set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad6676evb: Update to Vivado 2016.2
2016-08-30 13:08:07 +00:00
set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
set axi_ad6676_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad6676_cpack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad6676_cpack
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.ID {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad6676_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
# transceiver core
ad6676evb: Updated project to 2015.2.1 - updated to the new jesd framework - added cpack core
2015-09-25 11:44:46 +00:00
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_ad6676_xcvr
set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_ad6676_xcvr
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_ad6676_xcvr
set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_ad6676_xcvr
# reference clocks & resets
create_bd_port -dir I rx_ref_clk_0
ad6676evb: Updated project to 2015.2.1 - updated to the new jesd framework - added cpack core
2015-09-25 11:44:46 +00:00
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_*
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
ad_connect sys_cpu_resetn util_ad6676_xcvr/up_rstn
ad_connect sys_cpu_clk util_ad6676_xcvr/up_clk
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (adc)
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
ad_connect axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof
ad_connect axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk
ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst
ad_connect axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0
ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0
ad_connect axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0
ad_connect axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1
ad_connect axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1
ad_connect axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1
ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
ad_connect axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid
ad_connect axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync
ad_connect axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad6676_core
ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd
ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_xcvr/m_axi
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (adc)
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad6676_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad6676_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad6676_dma/irq