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pluto_hdl_adi/projects/ad9265_fmc/common/ad9265_bd.tcl

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Tcl
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ad9265: Initial commit
2014-09-24 02:51:42 +00:00
# ad9265
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_data_or_p
create_bd_port -dir I adc_data_or_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_p
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
# adc peripheral
set axi_ad9265 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9265:1.0 axi_ad9265]
set axi_ad9265_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9265_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9265_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9265_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9265_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
# clock for ila
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 12:49:29 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
# connections (ad9265)
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_connect adc_clk_in_p axi_ad9265/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9265/adc_clk_in_n
ad_connect adc_data_in_n axi_ad9265/adc_data_in_n
ad_connect adc_data_in_p axi_ad9265/adc_data_in_p
ad_connect adc_data_or_p axi_ad9265/adc_or_in_p
ad_connect adc_data_or_n axi_ad9265/adc_or_in_n
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 12:49:29 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_connect ad9265_clk axi_ad9265/adc_clk
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_connect ad9265_clk axi_ad9265_dma/fifo_wr_clk
ad_connect sys_200m_clk axi_ad9265/delay_clk
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 12:49:29 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_connect axi_ad9265/adc_valid axi_ad9265_dma/fifo_wr_en
ad_connect axi_ad9265/adc_data axi_ad9265_dma/fifo_wr_din
ad_connect axi_ad9265/adc_dovf axi_ad9265_dma/fifo_wr_overflow
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
# address mapping
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_cpu_interconnect 0x44A00000 axi_ad9265
ad_cpu_interconnect 0x44A30000 axi_ad9265_dma
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
# interconnect (adc)
ad9265: Changed the dma clock
2015-04-02 19:27:55 +00:00
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad9265_dma/m_dest_axi
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_connect sys_cpu_resetn axi_ad9265_dma/m_dest_axi_aresetn
# interrupts
ad9265: Initial commit
2014-09-24 02:51:42 +00:00
ad9265_fmc: Updated project to the new flow
2015-03-24 08:37:06 +00:00
ad_cpu_interrupt ps-13 mb-13 axi_ad9265_dma/irq