pluto_hdl_adi/projects/daq2/a10gx/system_constr.sdc

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2015-06-01 14:59:33 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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