pluto_hdl_adi/projects/fmcadc2/vc707/system_bd.tcl


source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl

p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18

source ../common/fmcadc2_bd.tcl
renamed to match official names 2014-12-08 15:44:15 +00:00
			`source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl`
			`source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl`

fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells. This is a the maximum BRAM FIFO depth in case of the VC707. 2015-04-23 14:56:35 +00:00			`p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18`
renamed to match official names 2014-12-08 15:44:15 +00:00
			`source ../common/fmcadc2_bd.tcl`